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riscv / riscv-test-env

https://jira.riscv.org/browse/RVG-141
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enable vector unit in V environment #20

Closed HanKuanChen closed 4 years ago

HanKuanChen commented 4 years ago

Follow convention, undefine RVTEST_VECTOR_ENABLE when V environment is enable. Otherwise, an illegal instruction exception will be raised.

aswaterman commented 4 years ago

In the long term, we'll need to deal with the fact that some V implementations do not have the F extension. For now, this is OK.