Unconditionally clear mie register while disabling interrupts.

riscv / riscv-test-env

https://jira.riscv.org/browse/RVG-141

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Unconditionally clear mie register while disabling interrupts. #26

Closed SandeepRajendran closed 4 years ago

SandeepRajendran commented 4 years ago

On systems without the delegation registers, this code sequence would end up skipping the csrw to mie. The right thing to do is move it before the attempted write to the delegation registers.

SandeepRajendran commented 4 years ago

@aswaterman , please review this.

aswaterman commented 4 years ago

LGTM, thanks.