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riscv / riscv-test-env

https://jira.riscv.org/browse/RVG-141
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Vector macro assumes floating point #36

Closed marcfedorow closed 2 years ago

marcfedorow commented 2 years ago

https://github.com/riscv/riscv-test-env/blob/34a1175291f9531e85afdb89aaa77707f45fc8e4/p/riscv_test.h#L145

This will fail on -march=rv64iv because csrwi fcsr, 0 is an illegal instruction due to absence of misa.F. If I understand correctly, riscv-v-spec does not assume the presence of floating point, i.e. misa.V does not imply misa.F. I suggest rename this macro to RVTEST_FP_VECTOR_ENABLE and use it in RVTEST_RV[xlen]UFV, and create macros for vector without FP.

aswaterman commented 2 years ago

Quoth the spec, "The V extension depends upon the F and D extensions" -- RV64IV is the same as RV64IFDV.

It's true that this would break for Zve32x or Zve64x, but the test environments just don't currently support those extensions.

marcfedorow commented 2 years ago

Quoth the spec, "The V extension depends upon the F and D extensions" -- RV64IV is the same as RV64IFDV.

Oh, I was not attentive enough. I'll add the V implies FD logic to spike, if everybody is OK woth it.

aswaterman commented 2 years ago

@marcfedorow Yeah, I'd appreciate you correcting that oversight.