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riscv / riscv-v-spec

Working draft of the proposed RISC-V V vector extension
https://jira.riscv.org/browse/RVG-122
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Best way to load/store a mask register? #315

Closed kito-cheng closed 4 years ago

kito-cheng commented 4 years ago

Does here any better way to load / store a mask register without changing vl and vtype? 

li t0, -1
vsetvli x0, t0, e32 # Set VL to VLMAX
vle.v  v0, (t1) # Load masking to v0

Compiler need that operation to spill a mask register.

aswaterman commented 4 years ago

I think that’s it. Or, in prologue/epilogue code, you spill/fill it as part of a larger block of registers (e.g. spill all of v0-v7).

On many machines, the extra vsetvli won’t matter too much, and spilling mask registers shouldn’t be super common, so I think this is OK.

On Mon, Nov 4, 2019 at 12:57 AM Kito Cheng notifications@github.com wrote:

Does here any better way to load / store a mask register without changing vl and vtype?

li t0, -1 vsetvli x0, t0, e32 # Set VL to VLMAX vle.v v0, (t1) # Load masking to v0

Compiler need that operation to spill a mask register.

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