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riscv / riscv-v-spec

Working draft of the proposed RISC-V V vector extension
https://jira.riscv.org/browse/RVG-122
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vsetvl x0, x0, * instruction limits #722

Open rjiejie opened 3 years ago

rjiejie commented 3 years ago

From vector spec https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#avl-encoding we know that "vsetvli x0,x0,*" allows the vtype register to be changed while maintaining the current vl, provided VLMAX is not reduced.

From compiler view, we need a instruction to set VLMAX without wasting any register. I mean whether we should remove the reserved limits ? it should allow VLMAX to shrink.

The vl value could be reduced by this instruction if the new SEW/LMUL ratio causes VLMAX to shrink, and so this case has been reserved as it is not clear this is a generally useful operation, and implementations can otherwise assume vl is not changed by this instruction to optimize their microarchitecture.

Some pattern of GCC like "mov" SPN can not guarantee this constraint in some context, so we need to call "vsetvli rd,x0,*" explicitly, it will waste a unused register :(

aswaterman commented 3 years ago

Have you got quantitative evidence that eliminating the wasted register has a material code size or performance impact in practice? (In any case, this would be a new instruction as part of a future extension, not part of 1.0.)

Note also, we defined whole-register move instructions that aren't affected by vtype/vl especially for this kind of situation. It's possible that you don't need any vsetvli instruction.