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riscv / riscv-v-spec

Working draft of the proposed RISC-V V vector extension
https://jira.riscv.org/browse/RVG-122
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What is the destination value beyond the tail for compare instruction under tail agnostic? #932

Open larryrong opened 9 months ago

larryrong commented 9 months ago

Hello,

I have a question about issue #602. This issue mentions that the "renamed implementations" will be simplified when the agnostic approach is adopted. https://github.com/riscv/riscv-v-spec/issues/602

I believe that the tail agnostic scheme simplifies a scenario when LMUL=8, SEW=8. In other cases, since the result does not overwrite a full vector register, bits beyond VLMAX should retain their original value, right? I believe we need to optimize mask register implementations and provide further details about the bits beyond VLMAX. If we wish to keep the current specification definition, the mask instruction must merge the result with the original data when VLMAX ≠ VLENB.

VLEN=64, SEW=16, LMUL=2, VLMAX=8, vl=4. vta=1
va = 'h00000000_12345678
vmseq va, vb, vc            # bit[3:0] will be updated according to setting. let 4-bit result to 4'he
va = 'h00000000_123456FX    # 8'b78->8'hfe, bits beyond VLMAX retain their original value. Is it correct for bits beyond VLMAX?

Thanks, Larry

sorear commented 7 months ago

The destination value under agnostic is either constant '1' or the old value in the register. This is given in §3.4.3.

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