riscv / riscv-zalasr

The ISA specification for the Zalasr extension.
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Require alignment exceptions? #2

Closed hboehm closed 1 year ago

hboehm commented 1 year ago

The "A" extension documentation currently says

"For AMOs, the A extension requires that the address held in rs1 be naturally aligned to the size of the operand (i.e., eight-byte aligned for 64-bit words and four-byte aligned for 32-bit words). If the address is not naturally aligned, an address-misaligned exception or an access-fault exception will be generated. The access-fault exception can be generated for a memory access that would otherwise be able to complete except for the misalignment, if the misaligned access should not be emulated. The "Zam" extension, described in Chapter 23, relaxes this requirement and specifies the semantics of misaligned AMOs."

I read that as requiring exceptions for misaligned accesses, unless the Zam extension is supported. If the Zam extension is not supported, an exception must be raised for a misaligned access even if atomicity could be easily supported. And I think that's correct. I would rather such code fail consistently rather than only occasionally, depending on cache-line alignment.

So I would vote for requiring the same behavior here.

mehnadnerd commented 1 year ago

I've changed it to match. https://github.com/mehnadnerd/riscv-zalasr/commit/8c0bd9565fae412b02902b7f555d1f7d53800265