search

riscv / riscv-zilsd

Zilsd (Load/Store Pair for RV32) Fast-Track Extension
https://jira.riscv.org/browse/RVG-122
Creative Commons Attribution 4.0 International
7 stars 2 forks source link

Unclarity about whether load/store pair are interruptible or not #46

Open Silabs-ArjanB opened 2 weeks ago

Silabs-ArjanB commented 2 weeks ago

Hi,

Version 0.9.0 of the specification states:

It is implementation defined whether interrupts can also be taken during the sequence execution.

This note was completely clear. Unfortunately it has been removed from version 0.10, which now only has the following related remark (which is not fully clear)

These decomposed sequences are interruptible.

What does the 'are interruptible' really mean? The decomposed sequenced 'shall be' interruptible or 'are allowed but not mandated to be' interruptible?

tovine commented 2 weeks ago

I think it's the latter, so software must not rely on the sequences to not be interrupted, but hardware can of course treat them as not interruptible.