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Sail RISC-V model
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Configurable word size for test signature file output #111

Open MarcKarasek opened 3 years ago

MarcKarasek commented 3 years ago

Would like to have an option to dump the signature file used by the riscv-arch-test (riscof) in either 32 bit values or 64 bit values.

This is so the barrier of entry for using the riscv-arch-test suite is easier. Currently if you are on a RV64 dut, then the signature is dumped out as 64 bit values (writememh()) and the resulting signature needs to be post processed into 32 bit values to match what sail is generating.

jrtc27 commented 3 years ago

What signature file? There is no riscof integration in Sail, just a PR whose general approach I have issues with.

neelgala commented 3 years ago

The C-simulator of Sail uses the --test-signature cli to dump out a memory region of the test encapsulated between begin_signature and eng_signature labels. This is used here : https://github.com/riscv-non-isa/riscv-arch-test/blob/master/riscv-target/sail-riscv-c/device/rv32i_m/I/Makefile.include#L9

neelgala commented 3 years ago

spike has this option of +signature-granularity=<num-bytes-per-line> which allows the user to specify the number of bytes to be dumped per line of the signature file. Something similar if available in SAIL would be useful.

jrtc27 commented 3 years ago

Oh ok that thing (which also exists for the OCaml simulator, I might add). Making that configurable isn't hard.

MarcKarasek commented 3 years ago

At the end of a test case run in sail it generates a signature file (dump of memory) to the system.

I was told this was from sail.

On Mon, Oct 4, 2021 at 12:34 PM Jessica Clarke @.***> wrote:

What signature file? There is no riscof integration in Sail, just a PR whose general approach I have issues with.

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MarcKarasek commented 3 years ago

It is this option : riscv_sim_RV64 --test-signature=

This is what is run for a test case...

On Mon, Oct 4, 2021 at 12:34 PM Jessica Clarke @.***> wrote:

What signature file? There is no riscof integration in Sail, just a PR whose general approach I have issues with.

— You are receiving this because you authored the thread. Reply to this email directly, view it on GitHub https://github.com/riscv/sail-riscv/issues/111#issuecomment-933655544, or unsubscribe https://github.com/notifications/unsubscribe-auth/AD72ZM5VRDHIQ5OATAJLRIDUFHJSRANCNFSM5FJY3Z6A . Triage notifications on the go with GitHub Mobile for iOS https://apps.apple.com/app/apple-store/id1477376905?ct=notification-email&mt=8&pt=524675 or Android https://play.google.com/store/apps/details?id=com.github.android&referrer=utm_campaign%3Dnotification-email%26utm_medium%3Demail%26utm_source%3Dgithub.

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MarcKarasek commented 3 years ago

Great htat would help us out a lot in how the signatures are generated between RV32 and RV64 bit DUTs..

On Mon, Oct 4, 2021 at 1:05 PM Jessica Clarke @.***> wrote:

Oh ok that thing (which also exists for the OCaml simulator, I might add). Making that configurable isn't hard.

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abukharmeh commented 2 years ago

@MarcKarasek #136 was merged addressing this issue, so I think we can close this ?

MarcKarasek commented 2 years ago

ok I have been tied up with other issues .. But am now getting back to running riscof on our DUT..

On Mon, Mar 7, 2022 at 8:23 PM Ibrahim Abu Kharmeh @.***> wrote:

@MarcKarasek https://github.com/MarcKarasek This has landed in the master branch, so I think we can close this issue?

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