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riscv / sail-riscv

Sail RISC-V model
https://lists.riscv.org/g/tech-golden-model
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switch to disable tlbs #182

Open neelgala opened 2 years ago

neelgala commented 2 years ago

I believe there is some sort of a TLB like structure used in SAIL which prevents PTW to be triggered for each memory/instruction access. It would be beneficial if we can have a switch via the cli to disable the TLBs so that all memory/instruction accesses undergo a PTW by default.

This requirement comes from the SIG-ACT with regards to capturing ISA coverage for tests dealing with translation schemes.

martinberger commented 2 years ago

@neelgala Do you mean something like this: https://github.com/riscv/sail-riscv/blob/master/model/riscv_vmem_sv32.sail#L157