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32-bit vs. 34-bit physical addresses in RV32 (without/with Sv32) #378

Open rsnikhil opened 9 months ago

rsnikhil commented 9 months ago

'mem_read_priv()' [riscv_mem.sail, L180] declares the address argument as 'xlenbits'

But Sv32 phys mem addrs are 34 bits, not 32 (XLEN) bits.

If RV32 is configured WITHOUT Sv32, are phys addrs 32 bits or 34 bits?

If RV32 is configured WITH Sv32, but we are running at M (machine) privilege or with SBare vmem, we can only generate 32-bit addresses. Are these simply zero-extended to 34 bits?

allenjbaum commented 9 months ago

This is more of an ISA question than a Sail question. Without Smode, there is no way to generate more than 32 bits of address, so that's a requirement. With Smode (and SV32 enabled) OR (Mmode && mstatus.MPRV=1 && mstatus.PP != Mmode && SATP.mode !=bare) you can generate a 34 bit address. RISC-V physical addresses are always zero extended (VAs are sign extended) so the top 2 bits would be zero otherwise

On Mon, Dec 18, 2023 at 8:40 AM Rishiyur S. Nikhil @.***> wrote:

'mem_read_priv()' [riscv_mem.sail, L180] declares the address argument as 'xlenbits'

But Sv32 phys mem addrs are 34 bits, not 32 (XLEN) bits.

If RV32 is configured WITHOUT Sv32, are phys addrs 32 bits or 34 bits?

If RV32 is configured WITH Sv32, but we are running at M (machine) privilege or with SBare vmem, we can only generate 32-bit addresses. Are these simply zero-extended to 34 bits?

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rsnikhil commented 8 months ago

The question is, what should the Sail model do?

I think the current definition of physical addrs as 32 bits for RV32 is not correct. With the 32 bit setting, the Sail model cannot model implementations that populate memory above the 32-bit address mark.

allenjbaum commented 8 months ago

It's worse than that. Without VM enabled, you can only use 34 bit addressing in Mmode by setting MPRV and giving it a VA that translates to the PA you want (and taking all the precautions to ensure that traps aren't fatal) SATP has to point to a legal page table under those conditions; it can't be in bare mode (because in bare mode, the rest of SATP must be zero) and if I'm reading the spec 3.1.6.2 correctly, even then there are cases where Mmode can only access half of the 32b address space (specifically, in RV64, in MMode with SXL=32, all register operands are sign extended, not zero extended, and that would apply to address calculations)

On Tue, Jan 2, 2024 at 1:49 PM Rishiyur S. Nikhil @.***> wrote:

The question is, what should the Sail model do?

I think the current definition of physical addrs as 32 bits for RV32 is not correct. With the 32 bit setting, the Sail model cannot model implementations that populate memory above the 32-bit address mark.

— Reply to this email directly, view it on GitHub https://github.com/riscv/sail-riscv/issues/378#issuecomment-1874607773, or unsubscribe https://github.com/notifications/unsubscribe-auth/AHPXVJQGCU62ZFY6E6ZKBFDYMR6FTAVCNFSM6AAAAABAZZ6QNOVHI2DSMVQWIX3LMV43OSLTON2WKQ3PNVWWK3TUHMYTQNZUGYYDONZXGM . You are receiving this because you commented.Message ID: @.***>

rsnikhil commented 8 months ago

@allenjbaum I think you're discussing different points than the issue I am raising.

You're discussing the various ISA nuances of Sv32 translation (when it occurs, how it occurs, …), which his fine.

My point is is different, it’s about what happens to the final output of Sv32 translation: that is a 34-bit physical address, and the sail-riscv model currently assumes it is 32 bit.

allenjbaum commented 8 months ago

Oh, yes, I was just pointing out that the spec has some corner cases that I don't think have been thought through (e.g. are PAs sign extended or zero extended?) that are related. It gets even worse if XLEN is different between Mode and U/S mode, which Sail can't handle at all.

On Tue, Jan 2, 2024 at 7:28 PM Rishiyur S. Nikhil @.***> wrote:

@allanjbaum I think you're discussing different points than the issue I am raising.

You're discussing the various ISA nuances of Sv32 translation (when it occurs, how it occurs, …), which his fine.

My point is is different, it’s about what happens to the final output of Sv32 translation: that is a 34-bit physical address, and the sail-riscv model currently assumes it is 32 bit.

— Reply to this email directly, view it on GitHub https://github.com/riscv/sail-riscv/issues/378#issuecomment-1874806093, or unsubscribe https://github.com/notifications/unsubscribe-auth/AHPXVJX6B27UYZHPI3N4LELYMTF7LAVCNFSM6AAAAABAZZ6QNOVHI2DSMVQWIX3LMV43OSLTON2WKQ3PNVWWK3TUHMYTQNZUHAYDMMBZGM . You are receiving this because you commented.Message ID: @.***>