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riscv / sail-riscv

Sail RISC-V model
https://lists.riscv.org/g/tech-golden-model
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Implement Zicbom, Zicboz (cbo.flush, cbo.inval, cbo.zero) #455

Open Timmmm opened 2 months ago

Timmmm commented 2 months ago

Note that Zicbop (prefetch hints) does not need to be implemented because all it does is label some existing base instructions as prefetch hints.

Also I have not wired up the enable flags to the emulators because it is rather tedious (and will hopefully be replaced by riscv-config at some point).

github-actions[bot] commented 2 months ago

Test Results

712 tests  ±0   712 :white_check_mark: ±0   0s :stopwatch: ±0s   6 suites ±0     0 :zzz: ±0    1 files   ±0     0 :x: ±0 

Results for commit 3dfd09fe. ± Comparison against base commit 0e9850fe.

:recycle: This comment has been updated with latest results.

bacam commented 2 months ago

Note that Zicbop (prefetch hints) does not need to be implemented because all it does is label some existing base instructions as prefetch hints.

Shouldn't there be encoding and assembly information at least? It might also be useful to calculate the address and pass it to a built-in function so that it could be logged (e.g., to check that some code's prefetch instruction refers to the correct address), along with a comment noting that no exceptions are taken if something goes wrong.

Timmmm commented 2 months ago

Shouldn't there be encoding and assembly information at least? It might also be useful to calculate the address and pass it to a built-in function so that it could be logged (e.g., to check that some code's prefetch instruction refers to the correct address), along with a comment noting that no exceptions are taken if something goes wrong.

That's a good point... I think it can be a separate PR though if anyone wants to tackle it.