Replace some bits(12)s with csreg

riscv / sail-riscv

Sail RISC-V model

https://lists.riscv.org/g/tech-golden-model

Other

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Closed Timmmm closed 1 month ago

Timmmm commented 1 month ago

Very minor. Uses an existing type alias.

github-actions[bot] commented 1 month ago

712 tests ±0 712 :white_check_mark: ±0 0s :stopwatch: ±0s 6 suites ±0 0 :zzz: ±0 1 files ±0 0 :x: ±0

Results for commit 52841d86. ± Comparison against base commit e1242d85.