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riscv / sail-riscv

Sail RISC-V model
https://lists.riscv.org/g/tech-golden-model
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Sail-riscv uses only 1 cpu thread at a time thus slowing down the compilaton. #487

Closed Mudassir10X closed 5 months ago

Mudassir10X commented 6 months ago

The sail-riscv model uses gcc to compile the c_emulator riscv_sim_RV32/64. there is a flag in C_FLAGS in makefile:L188 as -flto due to which a warning appears during building sail-riscv, that is:

lto-wrapper: warning: using serial compilation of 12 LTRANS jobs

This is because only one CPU thread is being used at a time and this slows down the building of the model. This can be solved by using

-flto=auto