riscv / sail-riscv

Sail RISC-V model
https://lists.riscv.org/g/tech-golden-model
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Remove `vlenb` register #565

Closed Timmmm closed 3 weeks ago

Timmmm commented 1 month ago

The model contains

register vlenb  : xlenbits

However this register contains no state and simply returns a hardcoded value VLEN/8 which is fixed at implementation time (it can't vary at runtime.

We should replace it with a get_vlenb() function.