Open TommyMurphyTM1234 opened 2 years ago
This text (bold emphasis is mine):
The LiteX soft SoC, developed in MiGen/Python that VexRiscv can be - and often is - combined with scales from simple designs with UART or SPI, I2C to complex setups with Ethernet, USB, PCIe, DDR controllers etc.
on this page of the docs:
https://risc-v-getting-started-guide.readthedocs.io/en/latest/zephyr-introduction.html
is garbled/confusing - particularly the bit in bold - but I'm not in a position to suggest a correction myself unfortunately.
This text (bold emphasis is mine):
on this page of the docs:
https://risc-v-getting-started-guide.readthedocs.io/en/latest/zephyr-introduction.html
is garbled/confusing - particularly the bit in bold - but I'm not in a position to suggest a correction myself unfortunately.