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riscvarchive / riscv-binutils-gdb

RISC-V backports for binutils-gdb. Development is done upstream at the FSF.
GNU General Public License v2.0
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Update to 0.8-draft-20191004. #182

Closed Nelson1225 closed 4 years ago

Nelson1225 commented 4 years ago

Update the following three things according to the 0.8-draft-20191004 version of vector spec.

  1. Swap opcodes of vw[s]maccsu (0x111110 to 0x111111) and vw[s]maccus (0x111111 to 0x111110).

  2. Add floating-point narrowing conversion with jamming (vfncvt.rod.f.f.v).

  3. Changed assembler syntax to use w in operand suffix to distinguish double-width source vector register group.

Change the following instructions

vnsrl.v[v|x|i] vnsra.v[v|x|i] vnclipu.v[v|x|i] vnclip.v[v|x|i] vfncvt.xu.f.v vfncvt.x.f.v vfncvt.f.xu.v vfncvt.f.x.v vfncvt.f.f.v vfncvt.rod.f.f.v

to

vnsrl.w[v|x|i] vnsra.w[v|x|i] vnclipu.w[v|x|i] vnclip.w[v|x|i] vfncvt.xu.f.w vfncvt.x.f.w vfncvt.f.xu.w vfncvt.f.x.w vfncvt.f.f.w vfncvt.rod.f.f.w

kito-cheng commented 4 years ago

Could you split this commit into 3 individual commit, one commit one change would be easier tracking.

Nelson1225 commented 4 years ago

Thanks for the suggestion. I have split the original commit into three individual commits, and get binutils testsuites pass for each of them.