Closed Nelson1225 closed 4 years ago
There is an open issue where I ask about instruction format names. https://github.com/riscv/riscv-v-spec/issues/93 This did come up in one of the vector extension task group meetings, but it isn't a high priority issue so I don't think that Krste has tried to fix it yet.
There are two commits, the first one is used to support vector format for .insn directive, and the second one is used to support INSN_CLASS_F (F_AND_C and V_AND_F) for the instructions that use the FPR. The second commit should be a upstream issue rather than the vector specific issue, so I will send it to upstream first, and then backport it on the vector branch.
Vector instruction are based on the A-extension, and the A-ext instruction is based on R-type instruction. The OPIVI instruction is confusing, I suppose this type instruction is based on R-type, but the Rt field must be a signed immediate rather than a register. The vector memory unit-stride instructions have the same issue (lumop and sumop) as OPIVI. Currently, I use the register to represent the simm4 and [l|s]umop for OPIVI and unit-stride, that is,
// OPIVI (rs (rs1) is simm4) // x31 = 0x11111 = -1 (two's complement) .insn r 0x57, 0x3, 0x0, v11, x0, a3 .insn r 0x57, 0x3, 0x0, v11, x31, a3 // unit-stride (rt (rs2) = lumop and sumop) // x16 = 0x10000 .insn r LOAD_FP, 0x0, 0x0, v11, a2, x0 .insn r LOAD_FP, 0x0, 0x1, v11, a2, x16
// OPIVI vadd.vi v11,v13,0,v0.t vadd.vi v11,v13,-1,v0.t // unit-stride vlbu.v[ ]+v11,(a2),v0.t vlbuff.v[ ]+v11,(a2)
Thanks Best Regards Nelson