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riscvarchive / riscv-binutils-gdb

RISC-V backports for binutils-gdb. Development is done upstream at the FSF.
GNU General Public License v2.0
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The immediate range of alias instructions in the test set #203

Closed joy2myself closed 4 years ago

joy2myself commented 4 years ago

File: riscv-binutils-gdb/gas/testsuite/gas/riscv/vector-insns.s Line:1242, 1246, 1250, 1254

vmsltu.vi v4, v8, -15
vmsgeu.vi v4, v8, -15
vmsltu.vi v4, v8, -15, v0.t
vmsgeu.vi v4, v8, -15, v0.t

The range of the unsigned immediate in this four instructions is 1 to 16 according to v0.8 spec. The test case for lower bound should be 

vmsltu.vi v4, v8, 1
vmsgeu.vi v4, v8, 1
vmsltu.vi v4, v8, 1, v0.t
vmsgeu.vi v4, v8, 1, v0.t
aswaterman commented 4 years ago

The assembler is getting this right. The standard RISC-V assembly syntax accepts signed immediates even when the immediates represent unsigned quantities. For example, in the scalar RV32 assembly syntax, you can express the computation a0 = a0 < 0xfffffffe by writing sltiu a0, a0, -2.

The NOTE in the V spec you're referring to is just trying to explain what the immediate range represents; it's not dictating the assembly syntax.

joy2myself commented 4 years ago

Thank you for your reply. I'm implementing an Assembler for rvv-llvm. Should I use signed operand for these immediates if I want to pass these test cases?

aswaterman commented 4 years ago

Yeah, I would recommend following suit.

Nelson1225 commented 4 years ago

I think this PR is the same as the one mentioned in the riscv-v-spec closed issue (https://github.com/riscv/riscv-v-spec/issues/327). The riscv-v-spec issue should be resolved, so I prefer to close this one, too.

You can reopen this PR or create a new one if needed. Thanks.