Closed kito-cheng closed 4 years ago
I think they should be expanded to
00000000 <.text>: 0: 6e85c257 vmslt.vx v4,v8,a1 4: 76422257 vmnot.m v4,v4 8: 6a85c257 vmsltu.vx v4,v8,a1 c: 76422257 vmnot.m v4,v4
And vmnot.m v4, v4
= vmnand.mm v4, v4, v4
. I will create a PR after running the tests.
Thanks
This should be fixed with https://github.com/riscv/riscv-binutils-gdb/issues/206 in rvv-0.9.x branch :)
Change expansion for masked vmsge{u}.vx with temp register, https://github.com/riscv/riscv-binutils-gdb/pull/210
Fixed via #207
vmsge.vx and vmsgeu.vx will use extra register which not appear in the operand list, and not defined any where.
Testcase:
Objdump:
Command:
$ riscv64-unknown-elf-as x.s -o x.o -march=rv64gcv
$ riscv64-unknown-elf-objdump -d x.o