search

riscvarchive / riscv-binutils-gdb

RISC-V backports for binutils-gdb. Development is done upstream at the FSF.
GNU General Public License v2.0
147 stars 233 forks source link

The Zvamo and Zvlsseg should be included in the base V extension. #219

Closed Nelson1225 closed 4 years ago

Nelson1225 commented 4 years ago

According to the following description in vector spec, https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#8-vector-amo-operations-zvamo https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#78-vector-loadstore-segment-instructions-zvlsseg

The Zvamo and Zvlsseg are intended to be included in the base V extension. And the "intended" will be changed to "shall" recently. To avoid causing problems for other projects, we update the assembler to treat the architecture string "v_zvamo_zvlsseg" and "v" as the same for now. That is, users only need to enable V extension, and then the vector AMO and vector load/store segment instructions are enabled, too.

jim-wilson commented 4 years ago

The way that I would expect this to work is if you have zvlsseg then you have the vector registers and csr and hardware, even if you don't have the base vector instructions. So we don't need to worry about whether any v or zvbase has been selected. zvbase means that you have the regular vector instructions like vadd and others. So V is equivalent to zvbase and zvlsseg and zvamo. If you have just vbase, then you don't specify v, you only specify zvbase. Similarly, if you have just the vlsseg instructions, then you don't specify v you only specify zvlsseg. Except that we don't have a name for zvbase yet so we can't implement that part.

See for instance how the B extension support works on the riscv-bitmanip branch. I think the vector support should work the same way. So the B extension has zbb which are the base bitmanip instructions, and you can enable them by either listing b or zbb in the arch option, which is handled by INSN_CLASS_B_OR_ZBB. You can use B to enable all of the default parts of the B extension, or you can list the individual zb* extensions that you have, which does not necessarily have to include zbb.

Nelson1225 commented 4 years ago

The way that I would expect this to work is if you have zvlsseg then you have the vector registers and csr and hardware, even if you don't have the base vector instructions.

I also update the riscv_csr_class_check, too. We now allow only enabling the zvlsseg and zvamo, and then assembler won't issue the warning when the vector register and -mcsr-check is used.

So we don't need to worry about whether any v or zvbase has been selected. zvbase means that you have the regular vector instructions like vadd and others. So V is equivalent to zvbase and zvlsseg and zvamo. If you have just vbase, then you don't specify v, you only specify zvbase. Similarly, if you have just the vlsseg instructions, then you don't specify v you only specify zvlsseg. Except that we don't have a name for zvbase yet so we can't implement that part.

Thank you very much for clarifying this :) Now I know how to handle these.