Closed Nelson1225 closed 4 years ago
Looks like quite a few recent changes. The vlXr now have an optional eX. There are new vfrece7 and vfrsqrte7 instructions. The index values are now specified to stop at ei64 where as we went up to ei1024. There is a new vncvt alias. Some of the source/dest overlap rules have changed. That is just what I noticed. There might also be other changes in there I missed.
OK I will start to add these today.
The binutils 2.35 is released now, so I prefer to close this PR, and will create a new one to the rvv-1.0.x, which is based on the binutils 2.35.
There are some changes according to the vector v1.0 released spec,
Extend the VLR and VSR instruction, when is 2, 4, 8.
https://github.com/riscv/riscv-v-spec/commit/0fec0e257cca5e389a0e1774e7d5aaac729b4ad2#diff-4fa320b4e415eee7270590bb06607389R1923
Added element width hint to whole register loads/stores. (Encode EEW for VLRE)
https://github.com/riscv/riscv-v-spec/commit/20f673c9aef9ee2ee18a30db52b9a2c5d287deb5#diff-4fa320b4e415eee7270590bb06607389R1910
Remove Vector indexed instruction when EEW >= 128. https://github.com/riscv/riscv-v-spec/commit/0fec0e257cca5e389a0e1774e7d5aaac729b4ad2#diff-4fa320b4e415eee7270590bb06607389R1532
Add assembly pseudo instructions vncvt.x.x.v. https://github.com/riscv/riscv-v-spec/commit/2ab0b81ddc3476de734d1bfb065d04bb8730a36b#diff-4fa320b4e415eee7270590bb06607389R2682
Added reciprocal and reciprocal square-root estimate instruction. https://github.com/riscv/riscv-v-spec/commit/d35b23f1a2c2e8d2a13fba1fae52b84e75c6d483#diff-34bccafef6cfe01367796362310416dfR190
Added vrgatherei16 instruction. https://github.com/riscv/riscv-v-spec/commit/a67925038b653a75cd7eadb68b9915449941745d
Make vlmul bits contiguous in vtype. (done in the https://github.com/riscv/riscv-binutils-gdb/pull/222) https://github.com/riscv/riscv-v-spec/commit/b8cd98bc9467617b6653583116b2dfe9eefb2f51
...
Thanks Nelson