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riscvarchive / riscv-binutils-gdb

RISC-V backports for binutils-gdb. Development is done upstream at the FSF.
GNU General Public License v2.0
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RISC-V: Support pause instruction as a hint fence w,0. #233

Closed Nelson1225 closed 3 years ago

Nelson1225 commented 3 years ago

There is a problem here - Should we regard the pause instruction as an alias of hint fence? Here is the assembly syntax of fence instruction,

fence [i][o][r][w], [i][o][r][w]

The current assembler doesn't allow the pred and succ fields are set to 0. Therefore, if the pause is an alias of fence, then we will get fence w,unknown when the option "-Mno-aliases" is set to objdump.

On the other hand, should we accept that the pred and succ fields can be set to 0 by the assembly fence instruction? That is,

fence 0, w --> illegal for now, should this be legal? fence w, 0 --> same as above fence 0, 0 --> same as above

If it is accepted, then it's fine to regard the pause instruction as an alias.

However, this patch doesn't regard the pause as an alias, and the 0 pred and succ are not accepted for the assembly fence.

Nelson1225 commented 3 years ago

Here is the ISA spec PR, https://github.com/riscv/riscv-isa-manual/pull/398

aswaterman commented 3 years ago

IMO, we should always have allowed pred=0/succ=0; that was an oversight on my part.

I probably would have used - as the syntax instead of 0, but either works.

kito-cheng commented 3 years ago

IMO, we should always have allowed pred=0/succ=0; that was an oversight on my part.

I probably would have used - as the syntax instead of 0, but either works.

Both binutils and LLVM are only support iorw as operand, maybe we should also update https://github.com/riscv/riscv-asm-manual too?

Nelson1225 commented 3 years ago

We don't need this anymore, so I delete the PR.