gfavor
commented
1 year ago On Sun, Apr 23, 2023 at 5:44 PM YenHaoChen @.***> wrote:
An instruction causing the HPM counter to overflow will set the OF bit. Additionally, a CSRW instruction can clear the OF bit. Consider the counting event includes CSRW instructions. What is the value of the OF bit after an overflowing CSRW clearing the OF bit?
This can be tricky since an hpm counter can be incremented by an event that is or is not a direct result of an instruction execution. Many events typically aren't attributable to an instruction, or aren't immediately attributable to an instruction by the completion of its execution. The "occurrence" of these events is generally asynchronous to instruction execution itself. Events in general are implementation-specific and can be defined however they want to be defined.
The instret example excerpted below exemplifies what should happen when the instruction reads and/or writes a CSR that is affected by the instruction's execution (although it only specifies this required behavior for the instret CSR). Also, the Priv spec says "Any CSR write takes effect after the writing instruction has otherwise completed" (although this is referring to writes to the counter and event CSRs).
Then there is also this relevant general text in the section in the Unpriv spec on CSR ordering:
Each RISC-V hart normally observes its own CSR accesses, including its implicit CSR accesses, as performed in program order. In particular, unless specified otherwise, a CSR access is performed after the execution of any prior instructions in program order whose behavior modifies or is modified by the CSR state and before the execution of any subsequent instructions in program order whose behavior modifies or is modified by the CSR state. Furthermore, an explicit CSR read returns the CSR state before the execution of the instruction, while an explicit CSR write suppresses and overrides any implicit writes or modifications to the same CSR by the same instruction.
This implies a consistency of observation between the OF bits in the event CSRs and the OF bits in scountovf (e.g. reading OF=1 in the latter means a following read of the corresponding event CSR must also have OF=1). And a consistency of observation between the OF bits in the event CSRs and the count values in the counter CSRs.
Finally, coming back around to your question which is specifically about the case of an event that counts CSRW instructions: This looks to be directly analogous to the instret CSR case and the same comments made in the excerpt below could apply. But I say "could" because the event in question could be defined to meet the same side effect ordering guarantees that are required of the instret CSR, or could be defined otherwise.
Lastly, an "overflowing instruction" has the side effect of advancing an hpm counter and, if that counter overflows, of also setting the OF bit in the event CSR (which then is reflected in scountovf). So yes, setting the OF bit is a side-effect. In essence, the instruction has a set of side-effects. (This assumes the event is defined to be tightly synchronous with execution of the instruction like instret is, versus allowing a time lag between executing the instruction and advancing an hpm counter.)
Greg
The Zicsr specification says that the CSRW takes priority over the side
effects of instruction execution. Is setting the OF bit a side effect of an overflowing instruction? [image: image] https://user-images.githubusercontent.com/39526191/233875575-cebb09ef-39c8-4c80-a175-e331d20545cb.png
Thank you.
Best regards, Howard (Yen-Hao) Chen
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YenHaoChen
Hello @gfavor,
I want to understand the corner case behavior of the OF bit.
An instruction causing the HPM counter to overflow will set the OF bit. Additionally, a CSRW instruction can clear the OF bit. Consider the counting event includes CSRW instructions. What is the value of the OF bit after an overflowing CSRW clearing the OF bit?
The Zicsr specification says that the CSRW takes priority over the side effects of instruction execution. Is setting the OF bit a side effect of an overflowing instruction?
Thank you.
Best regards, Howard (Yen-Hao) Chen