Open JohnAZoidberg opened 3 years ago
The commits don't have negative impact, so I picked them onto the WIP branches for RiscvVirt here:
acpiview
can be run but without the corresponding QEMU changes it does not show anything.
Thanks @JohnAZoidberg . Yes, qemu changes are required for it to display.
@vlsunil has been working on implementing ACPI for RISC-V.
Branches:
* https://github.com/vlsunil/riscv-edk2/tree/virt_acpi * https://github.com/vlsunil/riscv-edk2-platforms/tree/virt * https://github.com/vlsunil/qemu/tree/virt-acpi
The latest PoC code is available in the below branches.
QEMU
https://github.com/ventana-micro-systems/RISC-V-qemu/tree/acpi_v1_aia_v2
Tianocore
https://github.com/ventana-micro-systems/RISC-V-edk2-platforms/tree/acpi_v1_aia_v1 https://github.com/ventana-micro-systems/RISC-V-edk2/tree/acpi_v1_aia_v1
Linux
https://github.com/ventana-micro-systems/RISC-V-Linux/tree/acpi_v1_aia_v1
Linux boots with multiple CPUs. ACPI support is available with AIA interrupt controllers.
These branches are still the latest? Do they require any special configuration/build flags in qemu/edk2/linux?
I'd like to test it and possibly set up CI for it.
Hi Daniel, the instructions to build and test are documented at https://github.com/riscv-non-isa/riscv-acpi/wiki/PoC-:-How-to-build-and-test-ACPI-enabled-kernel.
based on LPC feedback, I am working on enabling a new ACPI table to communicate optional things etc which is still being defined and has a dependency on config discovery.
@vlsunil has been working on implementing ACPI for RISC-V.
Branches: