Previously DTM only used hart 0. This now uses hart 0 for the memory accesses, but actually starts all harts by setting their $pc to _start and letting them resume (DTM probes to find out the number of harts).
Note that this code requires/assumes that all harts have the same XLEN as hart 0. If you don't think that's a good requirement, the code can be easily changed to support heterogenous XLENs, but it will take more simulation cycles.
Previously DTM only used hart 0. This now uses hart 0 for the memory accesses, but actually starts all harts by setting their $pc to _start and letting them resume (DTM probes to find out the number of harts).
Note that this code requires/assumes that all harts have the same XLEN as hart 0. If you don't think that's a good requirement, the code can be easily changed to support heterogenous XLENs, but it will take more simulation cycles.
This PR also updates debug_defines.h to match the current Debug Spec (https://github.com/riscv/riscv-debug-spec/commit/920ec9a69054aba8d69b2acfd06c067798e4c8d8)