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RISC-V Frontend Server
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dtm_t vs tsi_t: Multicore / multiple hart support missing for tsi_t #39

Open StellaCassandra opened 6 years ago

StellaCassandra commented 6 years ago

Rocketchip (@680f3b162047c1ac36390dcdf682815fc0b24ffe) configuration: DualCoreConfig (default, unmodified)

On spike -p2, a bare-metal program is executed by both harts simultaneously.

The rocket-chip emulator (Verilator) uses the dtm_t interface for emulation. Executing a bare-metal program all harts start again simultaneously.

The fpga-zynq (deprecated) and midas-zynq (active) projects depend upon the tsi_t interface for fpga tethering. Here, the same bare-metal program is only executed on hart 0. The other harts are disabled. Hence, the reset interrupt for the remaining harts is not sent!

StellaCassandra commented 6 years ago

The quick and dirty solution is to perform the MSIP for every hart (using the already defined constant):

void tsi_t::reset()
{
  uint32_t one = 1;
  for (int i = 0; i < NHARTS_MAX; ++i) {
      write_chunk(MSIP_BASE + i * sizeof(uint32_t), sizeof(uint32_t), &one);
  }
}

Given that my understanding of the frontend server is rather limited, I don't know whether there are other areas that need to be adjusted as well.

Though, this does solve my problem of the other harts not starting. My bare metal program now behaves as expected.