"Why RISC-V?" whitepaper

[mgielda]

Questions (attack vectors ;) ) I got from Thales R&T:

• ASIC technology is obsolete, no way to have a 28nm done using RISC-V (Si-Five is 180nm, RISC-V is unable to compete with a T2080)
• No support, no one provides support,
• That's open source, it's always moving, there is no professional support to have our 10 years support requirements.
• This is just a core: No I/O, that's useless, it's just for academic purposes
• What about interconnect? AXI is for ARM, what about IPR?
• How to have a DO178B certified system from all these generated cores?
• Chisel? What’s that? No one knows this language. VHDL is better.

If we can address those things, that's a good start.

[neilhand]

What follows is a Codasip perspective, I am sure other members have complementary or alternative views

On May 3, 2017, at 9:51 AM, Michael Gielda notifications@github.com wrote:

Questions (attack vectors ;) ) I got from Thales R&T:

ASIC technology is obsolete, no way to have a 28nm done using RISC-V (Si-Five is 180nm, RISC-V is unable to compete with a T2080)

Initial applications are in the IoT space for which there is plenty of performance in the >90nm nodes. That said customers are looking at higher nodes and we have done benchmarks in 16FF.

No support, no one provides support, Incorrect Codasip is one of several that has there own commercial and fully supported RISC-V implementations.

That's open source, it's always moving, there is no professional support to have our 10 years support requirements. RISC-V is not open source, RISC-V is an Open ISA. Commercial vendors define the support terms for their cores, and long term support is not an issue for any commercial vendor (Codasip, SynthaCore, Bluespec, ATSC, etc) This is just a core: No I/O, that's useless, it's just for academic purposes Everyone knows its about more than just the core - as such both the open opens (RocketChip generator) as well as commercial solutions offer way more. What about interconnect? AXI is for ARM, what about IPR? AMBA is an industry standard at this point, undefended of the ISA. Is is open(ish) and has a rich ecosystem. It is not tied in anyway to an ARM processor. How to have a DO178B certified system from all these generated cores? I am not familiar with this on. Chisel? What’s that? No one knows this language. VHDL is better. RISC-V dones not equal Chisel. Each vendor can chose how they wish to define their core - and within the foundation you can find every flavor.

If we can address those things, that's a good start.

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[mgielda]

Hi @neilhand, thanks for the input. Of course, remember these are not questions from an aggressive journalist. It's an honest attempt from a RISC-V enthusiast to predict what their less enthusiastic colleagues might say, based also on some initial feedback from said colleagues. So what we're looking for is a more in-depth explanations, since the short answers are of course well-known (and the person asking is aware that the issues are not really unsolvable, they are just being helpful by suggesting potential 'attack vectors').

I created a document for this, makes it easier to discuss: https://docs.google.com/document/d/1qGv5N_c1e8J2tbGpd22yKZlbDrz2-tpA43owKtudFK0/edit

Please use 'suggest' mode so that we can discuss changes before making them. @arunthomas @rickoco @jackckang I would appreciate your input as well. I know some of those questions have been answered before - separately I'll think about the content structure and how to align this with the FAQ and other items.