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RISC-V Profiles and Platform Specification
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ISA requirements #49

Closed mdchitale closed 3 years ago

mdchitale commented 3 years ago

This patch merges the ISA requirements as crafted by Greg and the existing architecture requirements in the spec.

Signed-off-by: Greg Favor gfavor@ventanamicro.com Signed-off-by: Mayuresh Chitale mchitale@ventanamicro.com

kumarsankaran commented 3 years ago

Merged. Thanks.

Regards

Kumar

From: mdchitale @.> Sent: Tuesday, August 31, 2021 9:15 AM To: riscv/riscv-platform-specs @.> Cc: Subscribed @.**> Subject:* [riscv/riscv-platform-specs] ISA requirements (#49)

This patch merges the ISA requirements as crafted by Greg and the existing architecture requirements in the spec.

Signed-off-by: Greg Favor @. Signed-off-by: Mayuresh Chitale @.

You can view, comment on, or merge this pull request online at:

https://github.com/riscv/riscv-platform-specs/pull/49 Commit Summary

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aswaterman commented 3 years ago

For what it's worth, some of these topics are contentious and shouldn't be assumed to sail through without a fight. cc @gfavor

aswaterman commented 3 years ago

In particular, requirements like "hardware support for all misaligned accesses" are entirely inappropriate, for two reasons:

atishp04 commented 3 years ago

Ageed. That's why it is only mandated for server extension. The base allows the hardware not to implement misaligned access. In fact, the base also requires the M-mode to handle misaligned load/store traps.

On Tue, Aug 31, 2021 at 12:33 PM Andrew Waterman @.***> wrote:

In particular, requirements like "hardware support for all misaligned accesses" are entirely inappropriate, for two reasons:

  • There is no functional problem with emulating them in an M-mode trap handler; it's a performance problem.
  • The entire concept of "hardware support" is vacuous. Are we trying to say e.g. that QEMU is not a valid implementation of this platform?

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-- Regards, Atish

aswaterman commented 3 years ago

Nevertheless, it seems inappropriate to mandate HW implementation, for both reasons I mentioned. At minimum, it implies that non-HW implementations like QEMU cannot conform to this spec, which is presumably not the intent.

Even setting that aside, mandating support for features that are readily emulated seems questionable to me, because it conflates a performance requirement for a functional one. Surely this platform is not going to mandate a minimum clock rate, IPC, or core count, right?