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RISC-V Profiles and Platform Specification
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PCI cache coherency #83

Closed jonmasters closed 2 years ago

jonmasters commented 2 years ago

Section 4.7.3.4 describes behavior for No_Snoop bit but does not prescribe DMA coherence as a requirement. It shoud.

jscheid-ventana commented 2 years ago

I think it may be implicit, that No_Snoop=0 must do the right thing as long as hart effective PMAs are consistent. Making more things explicit sounds fine to me.

The existing wording is to allow implementations to ignore No_Snoop (i.e., always snooping).

kumarsankaran commented 2 years ago

The idea is that when No_Snoop is 1, hardware does not manage cache coherency and software will need to manage it. So how about the following for a modified wording? Memory that is cacheable by harts may not be kept coherent by hardware when PCIe transactions to that memory are marked with a No_Snoop bit of one. On platforms that honor the No_Snoop bit, software must manage coherency on such memory. otherwise, software and DMA operations are hardware coherent and software coherency management is not required.

jonmasters commented 2 years ago

Perfect

On Fri, Mar 18, 2022 at 17:43 Kumar Sankaran @.***> wrote:

The idea is that when No_Snoop is 1, hardware does not manage cache coherency and software will need to manage it. So how about the following for a modified wording? Memory that is cacheable by harts may not be kept coherent by hardware when PCIe transactions to that memory are marked with a No_Snoop bit of one. On platforms that honor the No_Snoop bit, software must manage coherency on such memory. otherwise, software and DMA operations are hardware coherent and software coherency management is not required.

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kumarsankaran commented 2 years ago

Fixed. Thanks.