The "UART/Serial Console" section does not say what size memory accesses are required to work for UART registers. I recommend that support be required only for word-size (4-byte) accesses, and that other sizes may possibly fail with an access fault or bus error.
The AMBA Advanced Peripheral Bus (APB) does not support reads narrower than word-size, and before 2010 did not support writes narrower than word-size either. If we say that byte-size and/or halfword-size accesses must be supported, then it's debatable whether a UART connected through even a recent APB can actually conform. In any event, there may be other buses in use, standard or custom, that can perform only word-size accesses, like older APBs.
Word-size accesses are obviously sufficient for interacting with the UART, so I can see no reason for the platform spec to require that other access sizes be supported.
I agree, but wanted to make sure we also consider the possibility of making sub-word accesses have UNSPECIFIED (not UNDEFINED) behavior, which permits (but does not require) that bus errors be raised.
The "UART/Serial Console" section does not say what size memory accesses are required to work for UART registers. I recommend that support be required only for word-size (4-byte) accesses, and that other sizes may possibly fail with an access fault or bus error.
The AMBA Advanced Peripheral Bus (APB) does not support reads narrower than word-size, and before 2010 did not support writes narrower than word-size either. If we say that byte-size and/or halfword-size accesses must be supported, then it's debatable whether a UART connected through even a recent APB can actually conform. In any event, there may be other buses in use, standard or custom, that can perform only word-size accesses, like older APBs.
Word-size accesses are obviously sufficient for interacting with the UART, so I can see no reason for the platform spec to require that other access sizes be supported.