I am looking into some descriptions in RISC-V of self/cross-modifying code (SMC/CMC), which is (quoted from intel x86 manual vol 3A, 8.1.3 "Handling Self- and Cross-Modifying Code")
The act of a processor writing data into a currently executing code segment with the intent of executing that data as code is called self-modifying code.
...
The act of one processor writing data into the currently executing code segment of a second processor with the intent of having the second processor execute that data as code is called cross-modifying code.
Software with just-in-time compilers relies on such behaviors heavily, such as OpenJDK [1].
The current RISC-V port of OpenJDK (ported from its AArch64 port) also uses such techniques. Some instructions (nop, jal) running on some reader harts may get dynamically patched by other writer harts (Of course on Linux there is __riscv_flush_icache called after the CMC writing behavior). But it's unknown to me if the readers can observe a legal state, so I am searching if there are documents setting this patching behavior as legal, that is, patching these instructions would not make some reader harts observe an "undefined behavior".
I didn't see much in the riscv-spec so I went to our riscv-isa-manual github. Coming from the nearly same issue and its comment [2], I reached here, with finding [3]. I think it can reflect what I am searching for (it doesn't say the store operation rise up exceptions and clarifies the legality of the read is guaranteed to be in a clear state, without undefined behaviors, so I guess it might be an intel x86 alike statement as below that all instructions at runtime could be safely patched when they are properly aligned).
I can find statements from the arm-v8 manual that only nop, bl, b, isb alike several instructions could be safely cross-modified. No safety of cross-modifying other instructions is guaranteed, described in "B2.2.5 Concurrent modification and execution of instructions".
In [3] I found our statement got an update to To order older stores before younger instruction fetches, .... I don't know if the older stores description could implicitly reflect whether RISC-V supports the CMC/SMC behaviors. I am a little confused about this.
The question is simple: is it legal to execute SMC/CMC behaviors on any instruction, that no interesting unpredictable state could be observed, in RISC-V's spec for now?
Hi team,
I am looking into some descriptions in RISC-V of self/cross-modifying code (SMC/CMC), which is (quoted from intel x86 manual vol 3A, 8.1.3 "Handling Self- and Cross-Modifying Code")
Software with just-in-time compilers relies on such behaviors heavily, such as OpenJDK [1].
The current RISC-V port of OpenJDK (ported from its AArch64 port) also uses such techniques. Some instructions (nop, jal) running on some reader harts may get dynamically patched by other writer harts (Of course on Linux there is
__riscv_flush_icachecalled after the CMC writing behavior). But it's unknown to me if the readers can observe a legal state, so I am searching if there are documents setting thispatchingbehavior as legal, that is, patching these instructions would not make some reader harts observe an "undefined behavior".I didn't see much in the riscv-spec so I went to our
riscv-isa-manualgithub. Coming from the nearly same issue and its comment [2], I reached here, with finding [3]. I think it can reflect what I am searching for (it doesn't say the store operation rise up exceptions and clarifies the legality of the read is guaranteed to be in a clear state, without undefined behaviors, so I guess it might be an intel x86 alike statement as below that all instructions at runtime could be safely patched when they are properly aligned).I can find statements from the arm-v8 manual that only
nop,bl,b,isbalike several instructions could be safely cross-modified. No safety of cross-modifying other instructions is guaranteed, described in "B2.2.5 Concurrent modification and execution of instructions".In [3] I found our statement got an update to
To order older stores before younger instruction fetches, .... I don't know if theolder storesdescription could implicitly reflect whether RISC-V supports the CMC/SMC behaviors. I am a little confused about this.The question is simple: is it legal to execute SMC/CMC behaviors on any instruction, that no interesting unpredictable state could be observed, in RISC-V's spec for now?
Thank you in advance!
Best, Xiaolin
[1] http://cr.openjdk.java.net/~jrose/jvm/hotspot-cmc.html [2] https://github.com/riscv/riscv-isa-manual/issues/650#issuecomment-852737970 [3] https://github.com/riscv/riscv-platform-specs/commit/38d0b4b6618edfd5ac523e3748c369ed19a2d80d#diff-e2e67320afc3dbcf884d10778f562bfa141048bbccbf7be067df8813a55a66fdL131-L137