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riscvarchive / riscv-qemu

QEMU with RISC-V (RV64G, RV32G) Emulation Support
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Fix a bug when sfence.vma is passed (rs2) arguments #107

Closed heshamelmatary closed 6 years ago

heshamelmatary commented 6 years ago

If there is an instruction like "sfence.vma x0, xx" where xx != x0, the csr value (bit[31:20]) won't match 0x120.

funct7 value (at bit[31:25]) needs to be checked first.

michaeljclark commented 6 years ago

I'll take a look at this...

@sorear right, we need to implement TSR, TW and TVM

michaeljclark commented 6 years ago

@heshamelmatary you just added the opc check and re-pushed right? @sorear LGTM

michaeljclark commented 6 years ago

I raised https://github.com/riscv/riscv-qemu/issues/108 for TSR, TW and TVM. They can most certainly be addressed separately.

heshamelmatary commented 6 years ago

@michaeljclark Yes. Thanks for taking care of the other issues

michaeljclark commented 6 years ago

@heshamelmatary Okay thanks. I'll merge it.