Closed heshamelmatary closed 6 years ago
I'll take a look at this...
@sorear right, we need to implement TSR, TW and TVM
@heshamelmatary you just added the opc check and re-pushed right? @sorear LGTM
I raised https://github.com/riscv/riscv-qemu/issues/108 for TSR, TW and TVM. They can most certainly be addressed separately.
@michaeljclark Yes. Thanks for taking care of the other issues
@heshamelmatary Okay thanks. I'll merge it.
If there is an instruction like "sfence.vma x0, xx" where xx != x0, the csr value (bit[31:20]) won't match 0x120.
funct7 value (at bit[31:25]) needs to be checked first.