Closed michaeljclark closed 6 years ago
There is now a partial implementation of no-MMU support in riscv-qemu (currently traps on satp writes). We also disable mstatus.mpp for invalid modes (misa.S or misa.U need to be set to support S and U modes repectively) but we need to trap on s* CSRs when misa.S is clear and handle the misa.S no-MMU 'satp' hardwired to zero case.
This is fixed in master (https://github.com/riscv/riscv-qemu/commit/33e3bc8d77b6ce95e622bdc0fce622d35b7ee56c) so closing the issue
@aswaterman
Also s* CSRs should trap if misa.S is clear
See https://github.com/riscv/riscv-isa-manual/issues/141