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QEMU with RISC-V (RV64G, RV32G) Emulation Support
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Drop writes to satp and return 0 when misa.S is set and no MMU is present. #113

Closed michaeljclark closed 6 years ago

michaeljclark commented 6 years ago

@aswaterman

Also s* CSRs should trap if misa.S is clear

See https://github.com/riscv/riscv-isa-manual/issues/141

michaeljclark commented 6 years ago

There is now a partial implementation of no-MMU support in riscv-qemu (currently traps on satp writes). We also disable mstatus.mpp for invalid modes (misa.S or misa.U need to be set to support S and U modes repectively) but we need to trap on s* CSRs when misa.S is clear and handle the misa.S no-MMU 'satp' hardwired to zero case.

michaeljclark commented 6 years ago

This is fixed in master (https://github.com/riscv/riscv-qemu/commit/33e3bc8d77b6ce95e622bdc0fce622d35b7ee56c) so closing the issue