RISC-V Privileged ISA spec conformance fixes and cleanup

[michaeljclark]

This is a series of spec conformance bug fixes and code cleanups. We would like to get this series in after our core changes in v8.2.

• Implements WARL behavior for CSRs that don't support writes
• Improves specification conformance of the page table walker
  • Change access checks from ternary operator to if statements
  • Checks for misaligned PPNs
  • Disallow M-mode or S-mode from fetching from User pages
  • Adds reserved PTE flag check: W or W|X
  • Improves page walker comments and general readability
• Several trivial code cleanups to hw/riscv
  • Replacing hard coded constants with reference to enums or the machine memory maps.
• Adds bounds checks when writing device-tree to ROM
• Updates the cpu model to use a more modern interface

[michaeljclark]

Merging into riscv-all

[NonerKao]

Sorry for bringing this up again, but it seems that in target/riscv/op_helper.c's csr_read_helper function, the logic around ctr_en is still out-of-date: it depends on m[s|u]counteren registers. The branch is the riscv-all after #123, so it should be fairly new. I'll keep a side note to this thread in my upcoming perf patch.