Open msuozzo opened 6 years ago
There is no major compatibility issue because:
In previous spec versions the tval/badaddr CSRs (which have been renamed in priv v1.10) were only set on address faults in priv v1.9.1, however now they have to be set on all exceptions. It is legal to set them to 0 which is what we do now. We have an outstanding fix for this. See this commit "RISC-V: Clear mtval/stval on exceptions without info" on this branch:
At some point we should update target/riscv/translate.c
to place the instruction bits in tval for illegal instruction exceptions. I have a work-in-progress branch, but it needs debugging:
The minimal compliance for privileged ISA v1.10 is now in master (https://github.com/riscv/riscv-qemu/commit/67185dad16284467dba9b6159f9ec9ec53689582), which clears mtval
/stval
on exceptions without address info.
I've raised a new issue to add support for populating mtval
/stval
with instruction bytes on illegal instruction exceptions https://github.com/riscv/riscv-qemu/issues/141
I've rebased the WIP branch to master. This branch actually does the rename of badaddr
to tval
(the CSR number is the same). The rename should probably be split from the commit that adds support for populating tval
on illegal instructions: https://github.com/michaeljclark/riscv-qemu/commits/wip-mtval-illegal-inst (this needs testing, as I couldn't get linux to boot with the changes)
From the Priv 1.10 preface:
While
mtval
(Section 3.1.21) has been added (link), it isn't used yet (link).stval
(Section 4.1.11) is neither present nor used and it appears to be included in the Priv 1.10 spec (although it isn't mentioned in the change notes).Also, the Priv 1.11 draft currently adds
*tvalreg
registers for additional trap data passing.