Generate illegal instruction traps for s* CSR accesses if misa.S is not set

riscvarchive / riscv-qemu

QEMU with RISC-V (RV64G, RV32G) Emulation Support

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Generate illegal instruction traps for s* CSR accesses if misa.S is not set #126

Open michaeljclark opened 6 years ago

michaeljclark commented 6 years ago

misa.S indicates the machine supports S mode, and hence implements the s*CSRs, either returning the required values, or hard-coded to zero as specified.

However, if S-mode is not implemented, s* CSR accesses should generate illegal instruction traps.