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QEMU with RISC-V (RV64G, RV32G) Emulation Support
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RV64 mstatus/status: SXL and UXL are not correctly implemented #139

Open vsiles opened 6 years ago

vsiles commented 6 years ago

Hi ! The misa register correctly provides the value of MXL, but the mstatus/sstatus register do not provide a valid value for the SXL and UXL bits (which are always returned as 0). For example, the documentation states that:

For RV64 and RV128 systems, if S-mode is not supported, then SXL is hardwired to zero. Other-
wise, it is a WARL field that encodes the current value of S-XLEN. In particular, the implemen-
tation may hardwire SXL so that S-XLEN = M-XLEN.

In the case of the sifive_u machine, where Supervisor mode is implemented, 0 is incorrect. Hard-wiring it MXL seems a good option to have a legal value for the time being.

michaeljclark commented 6 years ago

Thanks for the bug report. Will look into this...

michaeljclark commented 6 years ago

SXL and UXL are not implemented at all.