Add RVE register bounds checks to Base ISA ('I'/'E') in translate.c

[michaeljclark]

To enforce misa.E, target/riscv/translate.c needs register bounds checks added for the Base ISA ('I'/'E') and to generate illegal instruction exceptions if 'E' is set in misa and regno >= 16.

All other extensions are already disallowed on 'E' processors. 'M', 'A', 'F', 'D' and 'C' will already generate illegal instruction exceptions if not present so we only need to add register bounds checks to the Base ISA ('I'/'E') opcodes.

After adding enforcement to translate.c we need to alter write_misa to allow setting the 'E' flag:

• https://github.com/riscv/riscv-qemu/blob/3a6776ce09f5fb0daaec71af1b00504782b14861/target/riscv/csr.c#L357-L362