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QEMU with RISC-V (RV64G, RV32G) Emulation Support
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Improve emulation of Sifive PRCI and UART Memory-Mapped Registers #154

Closed nategraff-sifive closed 6 years ago

nategraff-sifive commented 6 years ago

Store writes to Sifive PRCI registers while maintaining oscillator ready/lock bits

Emulate the UART IP (interrupt pending) register

michaeljclark commented 6 years ago

Great.

These two patches are simple and obvious fixes and it looks like they will also apply to master. In this branch/series, hw/riscv is pretty similar to upstream, however, several changes in target/riscv depend on earlier infrastructural changes (CSR overhaul) so we'll need some time to curate this branch for submission in pieces upstream. i.e. re-order patches with git-rebase and split this branch into a reviewed branch for submission upstream.

QEMU is in change freeze for the 3.0 release so we won't be submitting large changes upstream right now. After the QEMU 3.0 release, we will create a riscv-qemu-3.0 branch based on upstream and the contents of this branch, after we've rebased (at present, we are several weeks behind master). I have several other patches I need to merge here too.

Perhaps after we've merged these commits, instead of deleting sifive-prci, we could rebase that branch against master and go through the qemu-devel workflow (git format-patch, ./scripts/checkpatch.pl, git send-email)... It would be nice to have more folk posting patches upstream, and we can review them there (the QEMU process) instead of here. Ya, keep the branch around.

At the moment we still want to accumulate patches in the queue here (rebasing multiple branches is a PITA). Once it's in the queue, we can shuffle the order around. As these patches don't depend on any unreviewed patches they can be moved early in the queue, just after the reviewed patches, when we eventually make some PRs after QEMU 3.0 is released.