Read/write of CSR registers via GDB doesn't work

A recent change in GDB revealed that the read/write of CSR registers via GDB doesn't work:

https://sourceware.org/ml/gdb-patches/2018-07/msg00676.html

Example output of a GDB client connected to GDB server of qemu-system-riscv32 or qemu-system-riscv64:

(gdb) p $misa
$1 = <unavailable>

In riscv_cpu_gdb_read_register() and riscv_cpu_gdb_write_register() register numbers >= 65 are implemented, however we have (target/riscv/cpu.c):

static void riscv_cpu_class_init(ObjectClass *c, void *data)
{
[...]
    cc->gdb_read_register = riscv_cpu_gdb_read_register;
    cc->gdb_write_register = riscv_cpu_gdb_write_register;
    cc->gdb_num_core_regs = 65;

This prevents that these functions are used for these registers. Changing this to cc->gdb_num_core_regs = 4096 + 65 leads to various problems.

Read/write to unimplemented registers leads to a do_raise_exception_err() which terminates the simulation.

I fixed this with a hack and got another errror. There are locking issues with the iothread mutex (qemu_mutex_lock_iothread()).

I fixed this with a hack and got a stack overflow in (case 'g')

static int gdb_handle_packet(GDBState *s, const char *line_buf)
{
    CPUState *cpu;
    CPUClass *cc;
    const char *p;
    uint32_t thread;
    int ch, reg_size, type, res;
    uint8_t mem_buf[MAX_PACKET_LENGTH];

since 4096 + 64 registers seems to be quite a lot.

I think we need an XML description of the CSR registers. See also target/arm/gdbstub.c and gdb-xml/*.xml

riscvarchive / riscv-qemu

Read/write of CSR registers via GDB doesn't work #156