Open michaeljclark opened 6 years ago
Below is output from the tests in: https://github.com/michaeljclark/qemu-riscv-tests
The tests are limited to testing CLIC configuration, WARL behaviour, interrupt delivery via CLIC. We still need to add pre-emption tests (internal software based pre-emption tests by writing to clicintip, and external tests using GPIO agitation), and sync up with the verification team on the hardware/software test harness. The current test scripts check which machines QEMU supports to decide which tests can be run. On older version of QEMU, only the CLINT tests will run. Currently it is a very simple/pragmatic harness.
mjc@miqi:~/src/sifive/qemu-riscv-tests$ make check
> test-rv32-clint-timer-interrupt-sifive_e PASS
> test-rv32-clint-timer-interrupt-sifive_u PASS
> test-rv32-clint-vectored-interrupt-sifive_e PASS
> test-rv32-clint-vectored-interrupt-sifive_u PASS
> test-rv32-clint-timer-interrupt-sifive_ex PASS
> test-rv32-clint-timer-interrupt-sifive_ux PASS
> test-rv32-clint-vectored-interrupt-sifive_ex PASS
> test-rv32-clint-vectored-interrupt-sifive_ux PASS
> test-rv32-clic-configure-cfg-e-sifive_ex PASS
> test-rv32-clic-configure-cfg-u-sifive_ux PASS
> test-rv32-clic-configure-intcfg-e-sifive_ex PASS
> test-rv32-clic-configure-intcfg-u-sifive_ux PASS
> test-rv32-clic-configure-intie-e-sifive_ex PASS
> test-rv32-clic-configure-intie-u-sifive_ux PASS
> test-rv32-clic-timer-interrupt-sifive_ex PASS
> test-rv32-clic-timer-interrupt-sifive_ux PASS
> test-rv64-clint-timer-interrupt-sifive_e PASS
> test-rv64-clint-timer-interrupt-sifive_u PASS
> test-rv64-clint-vectored-interrupt-sifive_e PASS
> test-rv64-clint-vectored-interrupt-sifive_u PASS
> test-rv64-clint-timer-interrupt-sifive_ex PASS
> test-rv64-clint-timer-interrupt-sifive_ux PASS
> test-rv64-clint-vectored-interrupt-sifive_ex PASS
> test-rv64-clint-vectored-interrupt-sifive_ux PASS
> test-rv64-clic-configure-cfg-e-sifive_ex PASS
> test-rv64-clic-configure-cfg-u-sifive_ux PASS
> test-rv64-clic-configure-intcfg-e-sifive_ex PASS
> test-rv64-clic-configure-intcfg-u-sifive_ux PASS
> test-rv64-clic-configure-intie-e-sifive_ex PASS
> test-rv64-clic-configure-intie-u-sifive_ux PASS
> test-rv64-clic-timer-interrupt-sifive_ex PASS
> test-rv64-clic-timer-interrupt-sifive_ux PASS
Below are the tests invoked with verbose interrupt and CLIC tracing (VERBOSE=1 TRACE=intr
). The VERBOSE
flag shows the command invocations.
mjc@miqi:~/src/sifive/qemu-riscv-tests$ make check VERBOSE=1 TRACE=intr
> test-rv32-clint-timer-interrupt-sifive_e
+ qemu-system-riscv32 -nographic -d trace:riscv_trap,trace:sifive_clic_cfg,trace:sifive_clic_intcfg,trace:sifive_clic_intie,trace:sifive_clic_intip,trace:sifive_clic_irq -machine sifive_e -kernel build/bin/rv32/clint-timer-interrupt-sifive_e
2020@1533028252.015109:riscv_trap hart:0, async:1, cause:0x7, epc:0x20400036, tval:0x0, desc=m_timer
PASS
> test-rv32-clint-timer-interrupt-sifive_u
+ qemu-system-riscv32 -nographic -d trace:riscv_trap,trace:sifive_clic_cfg,trace:sifive_clic_intcfg,trace:sifive_clic_intie,trace:sifive_clic_intip,trace:sifive_clic_irq -machine sifive_u -kernel build/bin/rv32/clint-timer-interrupt-sifive_u
2025@1533028252.040029:riscv_trap hart:0, async:1, cause:0x7, epc:0x80000036, tval:0x0, desc=m_timer
PASS
> test-rv32-clint-vectored-interrupt-sifive_e
+ qemu-system-riscv32 -nographic -d trace:riscv_trap,trace:sifive_clic_cfg,trace:sifive_clic_intcfg,trace:sifive_clic_intie,trace:sifive_clic_intip,trace:sifive_clic_irq -machine sifive_e -kernel build/bin/rv32/clint-vectored-interrupt-sifive_e
2030@1533028252.066614:riscv_trap hart:0, async:1, cause:0x7, epc:0x20400042, tval:0x0, desc=m_timer
PASS
> test-rv32-clint-vectored-interrupt-sifive_u
+ qemu-system-riscv32 -nographic -d trace:riscv_trap,trace:sifive_clic_cfg,trace:sifive_clic_intcfg,trace:sifive_clic_intie,trace:sifive_clic_intip,trace:sifive_clic_irq -machine sifive_u -kernel build/bin/rv32/clint-vectored-interrupt-sifive_u
2035@1533028252.089101:riscv_trap hart:0, async:1, cause:0x7, epc:0x80000042, tval:0x0, desc=m_timer
PASS
> test-rv32-clint-timer-interrupt-sifive_ex
+ qemu-system-riscv32 -nographic -d trace:riscv_trap,trace:sifive_clic_cfg,trace:sifive_clic_intcfg,trace:sifive_clic_intie,trace:sifive_clic_intip,trace:sifive_clic_irq -machine sifive_ex -kernel build/bin/rv32/clint-timer-interrupt-sifive_e
2040@1533028252.111739:riscv_trap hart:0, async:1, cause:0x7, epc:0x20400036, tval:0x0, desc=m_timer
PASS
> test-rv32-clint-timer-interrupt-sifive_ux
+ qemu-system-riscv32 -nographic -d trace:riscv_trap,trace:sifive_clic_cfg,trace:sifive_clic_intcfg,trace:sifive_clic_intie,trace:sifive_clic_intip,trace:sifive_clic_irq -machine sifive_ux -kernel build/bin/rv32/clint-timer-interrupt-sifive_u
2045@1533028252.136271:riscv_trap hart:0, async:1, cause:0x7, epc:0x80000036, tval:0x0, desc=m_timer
PASS
> test-rv32-clint-vectored-interrupt-sifive_ex
+ qemu-system-riscv32 -nographic -d trace:riscv_trap,trace:sifive_clic_cfg,trace:sifive_clic_intcfg,trace:sifive_clic_intie,trace:sifive_clic_intip,trace:sifive_clic_irq -machine sifive_ex -kernel build/bin/rv32/clint-vectored-interrupt-sifive_e
2050@1533028252.161586:riscv_trap hart:0, async:1, cause:0x7, epc:0x20400042, tval:0x0, desc=m_timer
PASS
> test-rv32-clint-vectored-interrupt-sifive_ux
+ qemu-system-riscv32 -nographic -d trace:riscv_trap,trace:sifive_clic_cfg,trace:sifive_clic_intcfg,trace:sifive_clic_intie,trace:sifive_clic_intip,trace:sifive_clic_irq -machine sifive_ux -kernel build/bin/rv32/clint-vectored-interrupt-sifive_u
2055@1533028252.182408:riscv_trap hart:0, async:1, cause:0x7, epc:0x80000042, tval:0x0, desc=m_timer
PASS
> test-rv32-clic-configure-cfg-e-sifive_ex
+ qemu-system-riscv32 -nographic -d trace:riscv_trap,trace:sifive_clic_cfg,trace:sifive_clic_intcfg,trace:sifive_clic_intie,trace:sifive_clic_intip,trace:sifive_clic_irq -machine sifive_ex -kernel build/bin/rv32/clic-configure-cfg-e-sifive_e
2060@1533028252.193228:sifive_clic_cfg hart:0, nmbits:0, nlbits:0, nvbits:0
2060@1533028252.193249:sifive_clic_cfg hart:0, nmbits:0, nlbits:4, nvbits:0
2060@1533028252.193257:sifive_clic_cfg hart:0, nmbits:0, nlbits:4, nvbits:0
2060@1533028252.193264:sifive_clic_cfg hart:0, nmbits:0, nlbits:4, nvbits:1
2060@1533028252.193271:sifive_clic_cfg hart:0, nmbits:0, nlbits:4, nvbits:0
PASS
> test-rv32-clic-configure-cfg-u-sifive_ux
+ qemu-system-riscv32 -nographic -d trace:riscv_trap,trace:sifive_clic_cfg,trace:sifive_clic_intcfg,trace:sifive_clic_intie,trace:sifive_clic_intip,trace:sifive_clic_irq -machine sifive_ux -kernel build/bin/rv32/clic-configure-cfg-u-sifive_u
2065@1533028252.203664:sifive_clic_cfg hart:0, nmbits:0, nlbits:0, nvbits:0
2065@1533028252.203688:sifive_clic_cfg hart:0, nmbits:0, nlbits:4, nvbits:0
2065@1533028252.203697:sifive_clic_cfg hart:0, nmbits:0, nlbits:4, nvbits:0
2065@1533028252.203703:sifive_clic_cfg hart:0, nmbits:0, nlbits:4, nvbits:1
2065@1533028252.203710:sifive_clic_cfg hart:0, nmbits:2, nlbits:4, nvbits:0
PASS
> test-rv32-clic-configure-intcfg-e-sifive_ex
+ qemu-system-riscv32 -nographic -d trace:riscv_trap,trace:sifive_clic_cfg,trace:sifive_clic_intcfg,trace:sifive_clic_intie,trace:sifive_clic_intip,trace:sifive_clic_irq -machine sifive_ex -kernel build/bin/rv32/clic-configure-intcfg-e-sifive_e
2070@1533028252.217569:sifive_clic_intcfg mode:3 hart:0, irq:7, val:0
2070@1533028252.217597:sifive_clic_intcfg mode:3 hart:0, irq:7, val:240
2070@1533028252.217608:sifive_clic_intcfg mode:3 hart:0, irq:7, val:240
PASS
> test-rv32-clic-configure-intcfg-u-sifive_ux
+ qemu-system-riscv32 -nographic -d trace:riscv_trap,trace:sifive_clic_cfg,trace:sifive_clic_intcfg,trace:sifive_clic_intie,trace:sifive_clic_intip,trace:sifive_clic_irq -machine sifive_ux -kernel build/bin/rv32/clic-configure-intcfg-u-sifive_u
2075@1533028252.228556:sifive_clic_cfg hart:0, nmbits:2, nlbits:4, nvbits:0
2075@1533028252.228583:sifive_clic_intcfg mode:1 hart:0, irq:7, val:0
2075@1533028252.228599:sifive_clic_intcfg mode:1 hart:0, irq:7, val:127
PASS
> test-rv32-clic-configure-intie-e-sifive_ex
+ qemu-system-riscv32 -nographic -d trace:riscv_trap,trace:sifive_clic_cfg,trace:sifive_clic_intcfg,trace:sifive_clic_intie,trace:sifive_clic_intip,trace:sifive_clic_irq -machine sifive_ex -kernel build/bin/rv32/clic-configure-intie-e-sifive_e
2080@1533028252.244787:sifive_clic_intie mode:3 hart:0, irq:7, val:1
2080@1533028252.244816:sifive_clic_intie mode:3 hart:0, irq:7, val:0
2080@1533028252.244826:sifive_clic_intie mode:3 hart:0, irq:7, val:2
PASS
> test-rv32-clic-configure-intie-u-sifive_ux
+ qemu-system-riscv32 -nographic -d trace:riscv_trap,trace:sifive_clic_cfg,trace:sifive_clic_intcfg,trace:sifive_clic_intie,trace:sifive_clic_intip,trace:sifive_clic_irq -machine sifive_ux -kernel build/bin/rv32/clic-configure-intie-u-sifive_u
2085@1533028252.255870:sifive_clic_intie mode:1 hart:0, irq:7, val:1
2085@1533028252.255893:sifive_clic_intie mode:1 hart:0, irq:7, val:0
2085@1533028252.255903:sifive_clic_intie mode:1 hart:0, irq:7, val:2
PASS
> test-rv32-clic-timer-interrupt-sifive_ex
+ qemu-system-riscv32 -nographic -d trace:riscv_trap,trace:sifive_clic_cfg,trace:sifive_clic_intcfg,trace:sifive_clic_intie,trace:sifive_clic_intip,trace:sifive_clic_irq -machine sifive_ex -kernel build/bin/rv32/clic-timer-interrupt-sifive_e
2090@1533028252.267185:sifive_clic_cfg hart:0, nmbits:0, nlbits:2, nvbits:0
2090@1533028252.267205:sifive_clic_intie mode:3 hart:0, irq:7, val:1
2090@1533028252.267210:sifive_clic_intip mode:3 hart:0, irq:7, val:0
2090@1533028252.277241:sifive_clic_intip mode:3 hart:0, irq:7, val:1
2090@1533028252.277269:riscv_trap hart:0, async:0, cause:0x30800007, epc:0x2040006a, tval:0x0, desc=(clic-interrupt)
PASS
> test-rv32-clic-timer-interrupt-sifive_ux
+ qemu-system-riscv32 -nographic -d trace:riscv_trap,trace:sifive_clic_cfg,trace:sifive_clic_intcfg,trace:sifive_clic_intie,trace:sifive_clic_intip,trace:sifive_clic_irq -machine sifive_ux -kernel build/bin/rv32/clic-timer-interrupt-sifive_u
2095@1533028252.288833:sifive_clic_cfg hart:0, nmbits:0, nlbits:2, nvbits:0
2095@1533028252.288851:sifive_clic_intie mode:3 hart:0, irq:7, val:1
2095@1533028252.288856:sifive_clic_intip mode:3 hart:0, irq:7, val:0
2095@1533028252.298917:sifive_clic_intip mode:3 hart:0, irq:7, val:1
2095@1533028252.298948:riscv_trap hart:0, async:0, cause:0x30800007, epc:0x8000006a, tval:0x0, desc=(clic-interrupt)
PASS
> test-rv64-clint-timer-interrupt-sifive_e
+ qemu-system-riscv64 -nographic -d trace:riscv_trap,trace:sifive_clic_cfg,trace:sifive_clic_intcfg,trace:sifive_clic_intie,trace:sifive_clic_intip,trace:sifive_clic_irq -machine sifive_e -kernel build/bin/rv64/clint-timer-interrupt-sifive_e
2100@1533028252.323491:riscv_trap hart:0, async:1, cause:0x7, epc:0x20400036, tval:0x0, desc=m_timer
PASS
> test-rv64-clint-timer-interrupt-sifive_u
+ qemu-system-riscv64 -nographic -d trace:riscv_trap,trace:sifive_clic_cfg,trace:sifive_clic_intcfg,trace:sifive_clic_intie,trace:sifive_clic_intip,trace:sifive_clic_irq -machine sifive_u -kernel build/bin/rv64/clint-timer-interrupt-sifive_u
2105@1533028252.348013:riscv_trap hart:0, async:1, cause:0x7, epc:0x80000036, tval:0x0, desc=m_timer
PASS
> test-rv64-clint-vectored-interrupt-sifive_e
+ qemu-system-riscv64 -nographic -d trace:riscv_trap,trace:sifive_clic_cfg,trace:sifive_clic_intcfg,trace:sifive_clic_intie,trace:sifive_clic_intip,trace:sifive_clic_irq -machine sifive_e -kernel build/bin/rv64/clint-vectored-interrupt-sifive_e
2110@1533028252.370019:riscv_trap hart:0, async:1, cause:0x7, epc:0x20400042, tval:0x0, desc=m_timer
PASS
> test-rv64-clint-vectored-interrupt-sifive_u
+ qemu-system-riscv64 -nographic -d trace:riscv_trap,trace:sifive_clic_cfg,trace:sifive_clic_intcfg,trace:sifive_clic_intie,trace:sifive_clic_intip,trace:sifive_clic_irq -machine sifive_u -kernel build/bin/rv64/clint-vectored-interrupt-sifive_u
2115@1533028252.391693:riscv_trap hart:0, async:1, cause:0x7, epc:0x80000042, tval:0x0, desc=m_timer
PASS
> test-rv64-clint-timer-interrupt-sifive_ex
+ qemu-system-riscv64 -nographic -d trace:riscv_trap,trace:sifive_clic_cfg,trace:sifive_clic_intcfg,trace:sifive_clic_intie,trace:sifive_clic_intip,trace:sifive_clic_irq -machine sifive_ex -kernel build/bin/rv64/clint-timer-interrupt-sifive_e
2120@1533028252.416081:riscv_trap hart:0, async:1, cause:0x7, epc:0x20400036, tval:0x0, desc=m_timer
PASS
> test-rv64-clint-timer-interrupt-sifive_ux
+ qemu-system-riscv64 -nographic -d trace:riscv_trap,trace:sifive_clic_cfg,trace:sifive_clic_intcfg,trace:sifive_clic_intie,trace:sifive_clic_intip,trace:sifive_clic_irq -machine sifive_ux -kernel build/bin/rv64/clint-timer-interrupt-sifive_u
2125@1533028252.442403:riscv_trap hart:0, async:1, cause:0x7, epc:0x80000036, tval:0x0, desc=m_timer
PASS
> test-rv64-clint-vectored-interrupt-sifive_ex
+ qemu-system-riscv64 -nographic -d trace:riscv_trap,trace:sifive_clic_cfg,trace:sifive_clic_intcfg,trace:sifive_clic_intie,trace:sifive_clic_intip,trace:sifive_clic_irq -machine sifive_ex -kernel build/bin/rv64/clint-vectored-interrupt-sifive_e
2130@1533028252.466542:riscv_trap hart:0, async:1, cause:0x7, epc:0x20400042, tval:0x0, desc=m_timer
PASS
> test-rv64-clint-vectored-interrupt-sifive_ux
+ qemu-system-riscv64 -nographic -d trace:riscv_trap,trace:sifive_clic_cfg,trace:sifive_clic_intcfg,trace:sifive_clic_intie,trace:sifive_clic_intip,trace:sifive_clic_irq -machine sifive_ux -kernel build/bin/rv64/clint-vectored-interrupt-sifive_u
2137@1533028252.488195:riscv_trap hart:0, async:1, cause:0x7, epc:0x80000042, tval:0x0, desc=m_timer
PASS
> test-rv64-clic-configure-cfg-e-sifive_ex
+ qemu-system-riscv64 -nographic -d trace:riscv_trap,trace:sifive_clic_cfg,trace:sifive_clic_intcfg,trace:sifive_clic_intie,trace:sifive_clic_intip,trace:sifive_clic_irq -machine sifive_ex -kernel build/bin/rv64/clic-configure-cfg-e-sifive_e
2142@1533028252.499944:sifive_clic_cfg hart:0, nmbits:0, nlbits:0, nvbits:0
2142@1533028252.499969:sifive_clic_cfg hart:0, nmbits:0, nlbits:4, nvbits:0
2142@1533028252.499979:sifive_clic_cfg hart:0, nmbits:0, nlbits:4, nvbits:0
2142@1533028252.499987:sifive_clic_cfg hart:0, nmbits:0, nlbits:4, nvbits:1
2142@1533028252.499995:sifive_clic_cfg hart:0, nmbits:0, nlbits:4, nvbits:0
PASS
> test-rv64-clic-configure-cfg-u-sifive_ux
+ qemu-system-riscv64 -nographic -d trace:riscv_trap,trace:sifive_clic_cfg,trace:sifive_clic_intcfg,trace:sifive_clic_intie,trace:sifive_clic_intip,trace:sifive_clic_irq -machine sifive_ux -kernel build/bin/rv64/clic-configure-cfg-u-sifive_u
2156@1533028252.511721:sifive_clic_cfg hart:0, nmbits:0, nlbits:0, nvbits:0
2156@1533028252.511750:sifive_clic_cfg hart:0, nmbits:0, nlbits:4, nvbits:0
2156@1533028252.511759:sifive_clic_cfg hart:0, nmbits:0, nlbits:4, nvbits:0
2156@1533028252.511767:sifive_clic_cfg hart:0, nmbits:0, nlbits:4, nvbits:1
2156@1533028252.511774:sifive_clic_cfg hart:0, nmbits:2, nlbits:4, nvbits:0
PASS
> test-rv64-clic-configure-intcfg-e-sifive_ex
+ qemu-system-riscv64 -nographic -d trace:riscv_trap,trace:sifive_clic_cfg,trace:sifive_clic_intcfg,trace:sifive_clic_intie,trace:sifive_clic_intip,trace:sifive_clic_irq -machine sifive_ex -kernel build/bin/rv64/clic-configure-intcfg-e-sifive_e
2161@1533028252.526023:sifive_clic_intcfg mode:3 hart:0, irq:7, val:0
2161@1533028252.526052:sifive_clic_intcfg mode:3 hart:0, irq:7, val:240
2161@1533028252.526062:sifive_clic_intcfg mode:3 hart:0, irq:7, val:240
PASS
> test-rv64-clic-configure-intcfg-u-sifive_ux
+ qemu-system-riscv64 -nographic -d trace:riscv_trap,trace:sifive_clic_cfg,trace:sifive_clic_intcfg,trace:sifive_clic_intie,trace:sifive_clic_intip,trace:sifive_clic_irq -machine sifive_ux -kernel build/bin/rv64/clic-configure-intcfg-u-sifive_u
2166@1533028252.537549:sifive_clic_cfg hart:0, nmbits:2, nlbits:4, nvbits:0
2166@1533028252.537581:sifive_clic_intcfg mode:1 hart:0, irq:7, val:0
2166@1533028252.537594:sifive_clic_intcfg mode:1 hart:0, irq:7, val:127
PASS
> test-rv64-clic-configure-intie-e-sifive_ex
+ qemu-system-riscv64 -nographic -d trace:riscv_trap,trace:sifive_clic_cfg,trace:sifive_clic_intcfg,trace:sifive_clic_intie,trace:sifive_clic_intip,trace:sifive_clic_irq -machine sifive_ex -kernel build/bin/rv64/clic-configure-intie-e-sifive_e
2171@1533028252.551327:sifive_clic_intie mode:3 hart:0, irq:7, val:1
2171@1533028252.551390:sifive_clic_intie mode:3 hart:0, irq:7, val:0
2171@1533028252.551403:sifive_clic_intie mode:3 hart:0, irq:7, val:2
PASS
> test-rv64-clic-configure-intie-u-sifive_ux
+ qemu-system-riscv64 -nographic -d trace:riscv_trap,trace:sifive_clic_cfg,trace:sifive_clic_intcfg,trace:sifive_clic_intie,trace:sifive_clic_intip,trace:sifive_clic_irq -machine sifive_ux -kernel build/bin/rv64/clic-configure-intie-u-sifive_u
2176@1533028252.565292:sifive_clic_intie mode:1 hart:0, irq:7, val:1
2176@1533028252.565322:sifive_clic_intie mode:1 hart:0, irq:7, val:0
2176@1533028252.565334:sifive_clic_intie mode:1 hart:0, irq:7, val:2
PASS
> test-rv64-clic-timer-interrupt-sifive_ex
+ qemu-system-riscv64 -nographic -d trace:riscv_trap,trace:sifive_clic_cfg,trace:sifive_clic_intcfg,trace:sifive_clic_intie,trace:sifive_clic_intip,trace:sifive_clic_irq -machine sifive_ex -kernel build/bin/rv64/clic-timer-interrupt-sifive_e
2181@1533028252.577775:sifive_clic_cfg hart:0, nmbits:0, nlbits:2, nvbits:0
2181@1533028252.577799:sifive_clic_intie mode:3 hart:0, irq:7, val:1
2181@1533028252.577805:sifive_clic_intip mode:3 hart:0, irq:7, val:0
2181@1533028252.587836:sifive_clic_intip mode:3 hart:0, irq:7, val:1
2181@1533028252.587899:riscv_trap hart:0, async:0, cause:0x30800007, epc:0x2040006a, tval:0x0, desc=(clic-interrupt)
PASS
> test-rv64-clic-timer-interrupt-sifive_ux
+ qemu-system-riscv64 -nographic -d trace:riscv_trap,trace:sifive_clic_cfg,trace:sifive_clic_intcfg,trace:sifive_clic_intie,trace:sifive_clic_intip,trace:sifive_clic_irq -machine sifive_ux -kernel build/bin/rv64/clic-timer-interrupt-sifive_u
2186@1533028252.599654:sifive_clic_cfg hart:0, nmbits:0, nlbits:2, nvbits:0
2186@1533028252.599675:sifive_clic_intie mode:3 hart:0, irq:7, val:1
2186@1533028252.599681:sifive_clic_intip mode:3 hart:0, irq:7, val:0
2186@1533028252.609749:sifive_clic_intip mode:3 hart:0, irq:7, val:1
2186@1533028252.609819:riscv_trap hart:0, async:0, cause:0x30800007, epc:0x8000006a, tval:0x0, desc=(clic-interrupt)
PASS
PLEASE DO NOT MERGE - QEMU CLIC BETA TEST V1
Implements draft clic-spec (20180728)
QEMU CLINT/CLIC Test Cases
Adds two experimental machines
CLIC combined CLINT/CLIC memory map
Adds CLIC interrupt tracing (
-d trace:riscv_trap,...
)Notes / Limitations