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riscvarchive / riscv-qemu

QEMU with RISC-V (RV64G, RV32G) Emulation Support
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fix bug of pmp_hart_has_privs #163

Closed wxjstz closed 5 years ago

wxjstz commented 5 years ago

Because PMP is optional, but mandatorily enabled by default if present, this means all “portable” system software that switches mode from M to S or U mode, must have code to configure PMP. Note also the code linked above sets and restores the trap vector in case the PMP CSRs are not implemented and cause an illegal instruction exception. Technically the PMP CSRs should be hard-wired to zero if not implemented and they are WARL (Write Any Read Legal) so one should read back the value to check if PMP is actually present.

For a discussion of this, see: https://groups.google.com/a/groups.riscv.org/forum/#!topic/isa-dev/OFa8TSc_PNI

michaeljclark commented 5 years ago

Changes are merged here: https://github.com/riscv/riscv-qemu/commits/qemu-for-testing