fix bug of pmpcfg_csr_write/pmpcfg_csr_read

[wxjstz]

Configuration register under RV32: pmpcfg0/pmpcfg1/pmpcfg2/pmpcfg3.

Configuration register under RV64: pmpcfg0/pmpcfg2.

pmpcfg_csr_write/pmpcfg_csr_read calculates the index by the following expression:reg_index * sizeof(target_ulong)) + i

RV32-> [0,3] [4,7] [8,11] [12,15], this is ok

RV64-> [0,7] [16,23] ,this is error

So we need add this code.

[michaeljclark]

Thanks!

I will have to trust you on these changes until I have more tests. I am writing some tests. Do you have any pointers to open tests? Are you using these?

• https://github.com/riscv/riscv-tests/tree/master/benchmarks/pmp

I guess we can't really break anything here given you are likely using PMP but i'd like to verify against FPGA.

[michaeljclark]

Okay, your explanation sounds correct. I have some configuration code that handles the RV32/64 case. I will study the change and test... (if you have pointers to your own tests, please share)

It would be nice to add tracing so we can more easily verify. I will apply your patch.

Thanks, Michael.

[michaeljclark]

Your changes are here: https://github.com/riscv/riscv-qemu/commits/qemu-for-testing

thx