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riscvarchive / riscv-qemu

QEMU with RISC-V (RV64G, RV32G) Emulation Support
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fix counter-enable checks in ctr() #183

Closed xiw closed 5 years ago

xiw commented 5 years ago

The current code ignores mcounteren in U-mode. It should check both mcounteren and scounteren.

Section 3.1.17: "When the CY, TM, IR, or HPMn bit in the mcounteren register is clear, attempts to read the cycle, time, instret, or hpmcountern register while executing in S-mode or U-mode will cause an illegal instruction exception."

jim-wilson commented 5 years ago

Patches should be submitted upstream. This repo may not be maintained anymore.

xiw commented 5 years ago

Thanks - upstreamed.