riscvarchive / riscv-qemu

QEMU with RISC-V (RV64G, RV32G) Emulation Support
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hw/riscv/sifive_clint.c: avoid integer overflow in timecmp #187

Closed Fabien-Chouteau closed 5 years ago

Fabien-Chouteau commented 5 years ago

Writing a high value in timecmp leads to an integer overflow. This patch modifies the code to detect such case, and use the maximum integer value as the next trigger for the timer.

jim-wilson commented 5 years ago

I think this tree is not actively maintained anymore. If the clint support is upstream, then the patch should be submitted upstream. If the clint is not upstream, then we may want to create a sifive specific qemu tree to hold sifive specific patches before we upstream them, and then we can give multiple sifive people write access to that tree.

Fabien-Chouteau commented 5 years ago

Hi @jim-wilson ,

You mean the qemu-for-upstream branch of this repo?

jim-wilson commented 5 years ago

No, I mean https://www.qemu.org/contribute/

Fabien-Chouteau commented 5 years ago

Got it.

Thanks,