Can't generate timer interrupt

[LoveZJT]

I want to handle timer interrupt. To do it, I should set mtimecmp firstly. But I have read riscv-privileged-v1.10 and found that mtime and mtimecmp have been exposed as memory-mapped registers. So riscv-probe which was mentioned in wiki of riscv-qemu, failed to read time csr because it used instruction csrr. The manual also provides the code sequence to set mtimecmp:

# New comparand is in a1:a0.
li t0, -1
sw t0, mtimecmp # No smaller than old value.
sw a1, mtimecmp+4 # No smaller than new value.
sw a0, mtimecmp # New value.

And I think the address of mtime and mtimecmp depend on the platform, so I want to know their address in riscv-qemu. How could I find other manuals of riscv-qemu except wiki of riscv-qemu and doc in wiki.qemu.org?

Thx

[jim-wilson]

As you mentioned, the address is platform dependent, so the address qemu will use depends on the platform qemu is emulating. qemu has support for sifive_e and sifive_u which use the CLINT and sifive_ex and sifive_ux which use the CLIC. You can find addresses in the qemu source code, e.g look in hw/riscv. You can find addresses in the SiFive processor documentation. At sifive.com/documentation the core and chip docs have memory maps in them that give the location of memory mapped registers. The mtimecmp address will be in the CLINT or CLIC section depending on whcih target you are looking at.

[LoveZJT]

Thx