riscvarchive / riscv-qemu

QEMU with RISC-V (RV64G, RV32G) Emulation Support
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sifive fixes #60

Closed frantony closed 6 years ago

sorear commented 7 years ago

FYI, the sifive_board is intended to use raw-format kernels not ELF; I think I fixed that earlier but it got lost?

frantony commented 7 years ago

FYI, the sifive_board is intended to use raw-format kernels not ELF; I think I fixed that earlier but it got lost?

You are right. As opposed to many popular qemu boards sifive_board is not intended to use ELF kernels.

I have used qemu sifive_board for porting barebox bootloader to RISC-V (https://www.spinics.net/lists/u-boot-v2/msg28603.html).

At the moment I use my own RISC-V qemu board for software emulation and the hw/sifive_board: get entry point address from kernel image patch is useless.

I'll update pull request after a short while.

frantony commented 6 years ago

@sorear , @sagark

Please review updated pull request.

michaeljclark commented 6 years ago

This makes a lot of sense i.e. re-use tested code.

I hadn't seen this PR before (partially) adding interrupts to sifive_uart.c and i've moved the constants into sifive_uart.h. It still will be quite easy to re-apply these changes.

And we also now have this PR https://github.com/riscv/riscv-qemu/pull/84

The current implementation interrupts on RX if SIFIVE_UART_IE_RXWM is set (assumes default 0 watermark)

We also need to do these things at some point:

And we need linux/drivers/tty/serial/sifive_uart.c so we can test it as it is the console UART on the sifive_u500 board (however SBI in bbl will currently drive the SiFive UART in polled mode).