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QEMU with RISC-V (RV64G, RV32G) Emulation Support
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U54 #70

Closed mcnamarad1971 closed 6 years ago

mcnamarad1971 commented 6 years ago

Hi all,

I thought I'd kick off some discussion by issuing a pull request for U54 related code from my u54 branch to riscv-qemu? The

kind regards, Daire (daire.mcnamara@emdalo.com)

poweihuang17 commented 6 years ago

HI, is this cold related with Sifive's coreplex U54?

michaeljclark commented 6 years ago

Hi Daire,

Awesome! I'm quite keen to test this code...

I'm sure you'll be keen to have someone hammering on the code. Ideally, we can keep support for both priv-1.9.1 and priv-1.10 as I know it might take a while for some folk to move off priv-1.9.1 so it would be nice we can have them co-exist in the same code base rather than having different branches. I have a few test kernels so I might branch your repo and do some testing and work with you on this. I'm happy to do some testing and make this work for both privileged versions. I also have some changes that i'd like to merge... I don't mind to spend some time to help get this merged.

I'll ping you again when i've had a chance to test. If you have any special kernel config, commit ids or bbl version I should use to test, let me know... I'll try with the riscv-linux riscv-next branch...

Thanks, Michael

mcnamarad1971 commented 6 years ago

That all sounds great!

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From: Michael Clark notifications@github.com Sent: Tuesday, November 14, 2017 11:25:16 PM To: riscv/riscv-qemu Cc: Daire McNamara; Author Subject: Re: [riscv/riscv-qemu] U54 (#70)

Hi Daire,

Awesome! I'm quite keen to test this code...

I'm sure you'll be keen to have someone hammering on the code. Ideally, we can keep support for both priv-1.9.1 and priv-1.10 as I know it might take a while for some folk to move off priv-1.9.1 so it would be nice we can have them co-exist in the same code base rather than having different branches. I have a few test kernels so I might branch your repo and do some testing and work with you on this. I'm happy to do some testing and make this work for both privileged versions. I also have some changes that i'd like to merge... I don't mind to spend some time to help get this merged.

I'll ping you again when i've had a chance to test. If you have any special kernel config, commit ids or bbl version I should use to test, let me know... I'll try with the riscv-linux riscv-next branch...

Thanks, Michael

— You are receiving this because you authored the thread. Reply to this email directly, view it on GitHubhttps://github.com/riscv/riscv-qemu/pull/70#issuecomment-344434203, or mute the threadhttps://github.com/notifications/unsubscribe-auth/AMPF6ME7W2NqwGweoB1_UhfKQLv5LiiOks5s2iFcgaJpZM4QdQvl.

michaeljclark commented 6 years ago

Hi Daire, all

We spent quite a bit of time with your code, testing it, and we took your changes and added back support for priv-1.9.1 (so we don't break stuff for folk with existing riscv-qemu workflows). We have integrated all of your priv-1.10 changes (SATP/PMP, etc), and added device tree support to the priv-1.10 boards so that we can run existing priv-1.9.1 bbl/linux as well as running upstream priv-1.10 bbl/linux. This pull derived from your code also adds device tree support which is required by priv-1.10:

https://github.com/riscv/riscv-qemu/pull/71

All that's left is to integrate the TIM, the X16550 UART and the unicorn_u54 board. This should be pretty easy. You'll see we have refactored riscv_hart.c so that we don't use global variables in any of the devices, rather we set a soc property on each device which has a reference to RISCVHartArray which is a component of the machine. We did this so that the CLINT and PLIC can support SMP and are fully parameterizable. e.g. we can use the same code on multiple boards with different MMIO layouts by setting different base address properties.

It has a lot of code from your branch along with work we did to add E300/HiFive1 support.

Cheers, Michael

michaeljclark commented 6 years ago

I'm closing this PR. master has changed such that this PR won't merge. I've commented on PR https://github.com/riscv/riscv-qemu/pull/84

Thanks for the help. The PMP and Priv 1.10 changes from this PR are all merged and we now have a PLIC that has been tested with 16550a and VirtIO.

Essentially we just need L2 ITIM/DTIM and LIM forward ported to master. I can help with this when I get time, as i've got a copy of this PR locally.