Implement 1.9/1.10 privilege ISA support and add sifive_e300 board

[michaeljclark]

• Add privileged ISA v1.10 support (SATP, new VM modes, SUM and PMP).
• Retain support for privileged ISA 1.9.1 (default machine).
• Refactor timing and interrupts into a parameterizable CLINT.
• Add SMP support and improve board/SOC topology and configuration.
• Refactor CPU, board and SOC classes to match other QEMU architectures.
• Implement device tree configuration for the spike v1.10 board.
• Add initial PLIC implementation (requires testing).

Supported Boards

• spike_v1.9 - priv v1.9.1 (HTIF and config string, default)
• spike_v1.10 - priv v1.10 (HTIF and device tree)
• sifive_e300 - priv v1.10 (UART, HiFive1 compatible)
• sifive_u500 - priv v1.10 (UART and device tree, WIP/TODO)

Detailed Changelog

• Merge priv-1.10 satp VM changes by Daire McNamara and Ivan Griffin.
• Merge PMP implementation by Daire McNamara and Ivan Griffin.
• Add privileged ISA versioning for concurrent v1.9.1 and v1.10 support.
• Improve support for initialization of multiple CPU types comprised of different extensions, base and privileged ISA versions.
• Implement RISCVHartArray SOC component to hold SMP state for devices.
• Simplify existing timer code and move it into SiFiveCLINT (Core Local Interruptor) with parameterizable base addresses and SMP IPI support.
• Simplify existing board config string and kernel loading code.
• Rename riscv_board.c to spike_v1_09.c and change it to use the new RISCVHartArray and SiFiveCLINT SOC components.
• Drop sifive_board.c and add sifive_u500.c that uses RISCVHartArray and SiFiveCLINT SOC components. Device tree support needs to be added.
• Add sifive_e300.c board that implements a skeleton of the HiFive1/E300 with CLINT, PRCI, MMIO regions for AON, QSPI, PRCI, GPIO and PWM.
• Update sifive_uart.c to handle TXCTRL, RXCTRL, DIV register accesses.
• Add SMP support for SOC components such as the PLIC and CLINT.
• Make device implementations comply with QEMU object models by using object properties to couple components and configure MMIO apertures.
• Add initial parameterizable PLIC implementation.
• Add mcounteren and scounteren CSRs required by priv-1.10 and update handling for mstatus bits exposed in sstatus.
• Add spike_v1_10.c board that supports priv-1.10 and device tree.

Running the SiFive E300 SDK hello example:

$ qemu-system-riscv32 -nographic -machine sifive_e300 \
    -kernel freedom-e-sdk/software/hello/hello
core freq at 3276800 Hz
hello world!

Progam has exited with code:0x00000000

Booting priv-1.9.1 bbl/linux with spike v1.9.1 and HTIF (default):

$ qemu-system-riscv64 -nographic -kernel bbl-1.9

Booting priv-1.10 bbl/linux with spike v1.10, HTIF and device tree:

$ qemu-system-riscv64 -nographic -machine spike_v1.10 \
    -kernel bbl-1.10

Dumping the device tree for the priv-1.10 spike emulator:

$ qemu-system-riscv64 -machine spike_v1.10,dumpdtb=spike.dts
$ fdtdump spike.dts

Dumping the device tree for the sifive_u500 emulator:

$ qemu-system-riscv64 -machine sifive_u500,dumpdtb=u500.dts $ fdtdump u500.dts

[sagark]

Awesome! I'll take a look

[sagark]

Everything looks good to me! Could you update the README.md file to reflect the new features? Then I'll merge.

[michaeljclark]

Okay I've updated the readme to list both privilege spec versions and added a pointer to the commit id for current riscv-tools (v1.10), along with instructions on selecting the various boards... (spike_v1.9, spike_v1.10 and sifive_e300).

I'll follow up with some updates to sifive_u500. It's still under development as you know. We have three boards and two spec versions that can be used now so it should be a little easier for users, however they should ideally use the spike configuration.

Expect more pull requests soon...

[michaeljclark]

Thanks

[sagark]

Awesome, thanks!